Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device
Reexamination Certificate
2002-06-13
2003-11-11
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
Having specific type of active device
C257S202000
Reexamination Certificate
active
06646294
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration, particularly in a logic or digital circuit, having a plurality of transistors of two different conductivity types. The transistors are arranged in transistor rows, and the transistor rows are arranged at a distance from one another in succession along a direction of arrangement and alternately each contain only transistors of one of the two conductivity types. The transistors in each transistor row form groups such that a respective group of transistors of the first conductivity type has an associated group of transistors of the second conductivity type in an adjacent transistor row, the latter group forming a digital functional unit with this adjacent transistor row.
Such circuit configurations are obtained, by way of example, during automatic generation of “full custom layouts” using layout synthesis programs. These programs use, by way of example, circuit diagrams from cell libraries in order to make production of the layout for, by way of example, a logic or digital circuit automatable by using a limited number of basic building blocks. The individual transistors are thereby positioned and wired individually, in contrast to the “semi-custom” methodology, where the layouts for the library elements have already been firmly prescribed.
In CMOS technology, the N-channel transistors and the P-channel transistors are in this case positioned in separate rows and are connected to one another afterward. In this context, precisely one row of N-channel transistors and one row of P-channel transistors are respectively associated with one another. A group of N-channel transistors and a group of P-channel transistors in adjacent rows form a digital functional unit with one another, for example an inverter, a NOR gate, a NAND gate, a counter, a half-adder or the like.
Since the size and number of N-channel and P-channel transistors required are generally different in this case, empty areas are often obtained in individual rows. This is true particularly when different widths are used within a particular conductivity type.
Very wide transistors such as are often used, in particular, for P-channel transistors are also frequently split into a plurality of small transistors, which makes the numbers of N-channel and P-channel transistors even more different.
The empty areas described and the associated increased space requirement for the circuit configuration on the chip are naturally a drawback, given the scarce chip area, and need to be prevented as far as possible.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration with a plurality of transistors of different conductivity types, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which has a lower space requirement for the same functionality.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration, comprising:
a plurality of transistors of a first and a second conductivity type disposed in transistor rows, the transistor rows being formed with a spacing distance from one another, disposed in succession along a given direction, and alternately containing only transistors of a respective one of the conductivity types;
the transistors in each transistor row forming groups such that a respective group of transistors of the first conductivity type has an associated group of transistors of the second conductivity type in an adjacent transistor row, the associated group of transistors forming a digital functional unit with the respective group in the adjacent the transistor row;
wherein a first transistor row, a second transistor row, and a third transistor row each contain both a transistor group whose associated transistor group is arranged in the transistor row that is adjacent in the given direction and a transistor group whose associated transistor group is arranged in the transistor row that is adjacent in an opposite direction; and
wherein the second transistor row is arranged in the given direction between the first transistor row and the third transistor row and contains a transistor group that is associated with a transistor group in the first transistor row, and a transistor group that is associated with a transistor group in the third transistor row.
In other words, the invention is achieved in that a generic circuit configuration has at least one transistor row which contains both a transistor group whose associated transistor group is arranged in the transistor row which comes next in the direction of arrangement and a transistor group whose associated transistor group is arranged in the transistor row which comes previously in the direction of arrangement.
The invention is thus based on the concept of saving chip area overall by splitting the fixed row assignment of the functional units and by means of appropriate repositioning.
In accordance with a preferred embodiment with a particularly large gain in area, essentially all the transistor rows in the circuit configuration which contain transistors of the first conductivity type contain both a transistor group whose associated transistor group is arranged in the transistor row which comes next in the direction of arrangement and a transistor group whose associated transistor group is arranged in the transistor row which comes previously in the direction of arrangement.
In this case, the wording “essentially all the transistor rows” makes allowance for the fact that the edge rows have only one adjacent transistor row, that is to say cannot have groups associated both with the next row and with the previous row. Repositioning can also be ended if the maximum possible space gain for a particular arrangement has already been attained as a result of regroupings in previous transistor rows.
In another preferred embodiment, essentially all the transistor rows in the circuit configuration which contain transistors of the second conductivity type contain both a transistor group whose associated transistor group is arranged in the transistor row which comes next in the direction of arrangement and a transistor group whose associated transistor group is arranged in the transistor row which comes previously in the direction of arrangement.
It will be understood that the two embodiments can also be combined with one another.
In one particularly advantageous refinement of the invention, the at least one transistor row is split into two adjacent blocks such that the first block comprises only adjacent transistor groups whose associated transistor groups are arranged in the transistor row which comes next in the direction of arrangement, and the second block comprises only transistor groups whose associated transistor groups are arranged in the transistor row which comes previously in the direction of arrangement.
In the case of this area reduction concept, the affiliated transistor groups are pushed together to form larger blocks before they are repositioned. So that associated regions in adjacent rows come to be situated above one another even after repositioning, it may be necessary in this context for blocks containing associated groups to be interchanged with one another within their row.
A particularly large area gain is also obtained in this case if essentially all the transistor rows in the circuit configuration which contain transistors of the first conductivity type are split into two adjacent blocks such that the first block comprises only transistor groups whose associated transistor groups are arranged in the transistor row which comes next in the direction of arrangement, and the second block comprises only transistor groups whose associated transistor groups are arranged in the transistor row which comes previously in the direction of arrangement.
In particular, it is possible, even up to edge rows, for essentially all the transistor rows to be split into two adjacent blocks such that the first bloc
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
Wilson Allan R.
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