Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2001-06-18
2002-08-27
Martin, David S. (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S792000, C361S764000, C361S783000, C174S255000, C257S700000, C257S701000, C257S702000
Reexamination Certificate
active
06442042
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration having at least one nanoelectronic component and a method for fabricating the component.
In order to produce a circuit configuration with an ever higher packing density, dimensions of a component of the circuit configuration will probably measure just a few nanometers in the very foreseeable future. An example of such a so-called nanoelectronic component is a single-electron component in which circuit operations are realized by individual electrons. C. D. Chen et al., “Aluminium single-electron nonvolatile floating gate memory cell”, Appl. Phys. Lett. 71 (14) (1997) 2038 describes a single-electron transistor which is essentially produced from aluminum.
Nanoelectronic components may also be biological nerve cells or molecular-electronic structures (see e.g. C. M. Fischer et al., “Organic Quantum Wells: Molecular Rectification and Single-Electron Tunnelling”, Europhys. Lett. 28, 129 (1994)).
In general, nanoelectronic components are proposed which are fabricated using a very different technology from conventional CMOS components.
F. G. Pikus et al., “Nanoscale field-effect transistors: An ultimate size analysis”, Appl. Phys. Lett. 71 (25) (1997) 3661, investigate a nanoelectronic CMOS component.
K. Yano et al., “A Room-Temperature Single-Electron Memory Device Using Fine-Grain Polycrystalline Silicon”, IEDM (1993) 541, disclose a nanoelectronic memory cell including a transistor. Source, drain and channel regions of the transistor are produced by patterning an amorphous silicon layer having a thickness of 4 nm. Grains of the silicon layer have horizontal dimensions of approximately 10 nm. The channel region and a gate electrode of the transistor are surrounded by SiO
2
. If the transistor is operated with low current, then a narrow channel forms in the channel region, which channel includes a chain of grains between which individual electrons tunnel. The threshold voltage of the transistor can be changed analogously to an EEPROM, which corresponds to programming of the memory cell. In order to program e.g. a logic 1, the voltage at the gate electrode, which acts as control gate electrode, is increased to an extent such that electrons hop to grains of the channel region which lie outside the channel, and remain there. The charged grains act analogously to a floating gate electrode of the EEPROM, so that the threshold voltage of the transistor is altered.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration having at least one nanoelectronic component and a method for fabricating the circuit configuration which overcomes disadvantageous of the prior art apparatus and methods of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention a circuit configuration having at least one nanoelectronic component, in which the circuit configuration includes: a semiconductor substrate; and a CMOS circuit that is configured in the semiconductor substrate. The CMOS circuit includes at least one CMOS component. An insulating layer is configured on the semiconductor substrate and covers the CMOS component. A first nanoelectronic component is configured above the insulating layer. Conductive structures are configured in the insulating layer. At least one of the conductive structures connect the first nanoelectronic component to the CMOS component. A plurality of nano-switching blocks are configured above the insulating layer. Each one of the plurality of the nano-switching blocks are defined by a group of further nanoelectric components. Each one of the plurality of the nano-switching blocks has lines with RC times that interconnect the further nanoelectric components of the one of the plurality of the nano-switching blocks. Each one of the plurality of the nano-switching blocks has a size such that the RC times of the lines are not greater than 1 ns. A first drive circuit for the plurality of the nano-switching blocks is provided in which the first drive circuit is defined by the CMOS circuit. A plurality of second drive circuits is provided. Each one of the plurality of the nano-switching blocks is adjoined by a respective one of the plurality of the second drive circuits that is connected between the one of the plurality of the nano-switching blocks and the CMOS circuit. The conductive structures connect the CMOS circuit to the plurality of the second drive circuits. One of the plurality of the second drive circuits combines the lines of the one of the plurality of the nano-switching blocks such that a number of the conductive structures that are connected to the one of the second drive circuits is less than a number of the lines of the one of the plurality of the nano-switching blocks.
With the foregoing and other objects in view there is provided, in accordance with the invention a method for fabricating a circuit configuration, which includes steps of: providing a semiconductor substrate; using a CMOS method to produce at least one CMOS component in the semiconductor substrate; after producing the CMOS component, applying an insulating layer on the semiconductor substrate and covering the CMOS component with the insulating layer; producing a conductive structure in the insulating layer and connecting the conductive structure to the CMOS component; and using a nano-pattering technique to produce a nanoelectronic component above the insulating layer such that the nanoelectronic component is connected to the CMOS component by the conductive structure.
The circuit configuration has a high packing density since the CMOS component is configured under the nanoelectronic component.
The invention enables the integration of nanoelectronic components into microelectronic products.
Since the nanoelectronic component is not produced until after the CMOS component has been produced, it is not attacked by the method steps for producing the CMOS component. The nano-patterning technique may differ from the conventional CMOS methods.
In accordance with an added feature of the invention, the circuit configuration may include further nanoelectronic components. In order to increase the packing density, the nanoelectronic components are configured as close together as possible. For a given number of nanoelectronic components which are interconnected by lines, the dense configuration causes the lines to be shortened. This is advantageous since resistances of the lines are reduced. On the one hand, this means a smaller energy loss in the circuit configuration. On the other hand, the product of the resistance and the capacitance of the lines, the so-called RC time, is likewise small, so that changes in the voltages of the lines take place more quickly, and the circuit configuration switches more quickly.
In order to realize short lines despite a large number of nanoelectronic components, it is advantageous to group the nanoelectronic components into nano-switching blocks. A nano-switching block is a configuration of adjacent nanoelectronic components which are interconnected by lines having nanomete-wide cross sections. Although the grouping increases the number of lines of the circuit configuration, by the same token the lines are shorter. Furthermore, the grouping facilitates the dissipation of heat from the circuit configuration.
In accordance with an additional feature of the invention, the nano-switching blocks are each so small that the RC times of their lines are not longer than 1 ns. Using the conductive structure and further conductive structures configured in the insulating layer, the nano-switching blocks are connected to a CMOS circuit, which includes the CMOS component. Preferably, each nano-switching block is connected to the CMOS circuit through at least one of the conductive structures. A further advantage of the invention is manifested here: since the CMOS circuit is configured under the nano-switching blocks, and not beside them, for example, the conductive structures do not run in the two-
Ramcke Ties
Risch Lothar
Rösner Wolfgang
Bui Hung
Greenberg Laurence A.
Infineon - Technologies AG
Martin David S.
Mayback Gregory L.
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