Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2001-09-06
2003-02-11
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S118000, C341S155000, C341S169000
Reexamination Certificate
active
06518900
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to test circuits and more particularly relates to a circuit configuration for testing an A/D converter, especially for applications that are critical in terms of safety.
BACKGROUND OF THE INVENTION
Reliability and failsafe operation are of special importance in circuits for safety-critical applications and systems. It is especially significant to safeguard that in case of malfunction of one component the entire system will not be jeopardized. To reach this objective it is necessary to detect faults in the component concerned and to take appropriate measures.
One such component which must oftentimes be monitored in terms of failsafe operation is e.g. an A/D (analog/digital) converter. It is known in the art to operate two identical A/D converters in parallel, to monitor the output signals of both converters for equality, and to produce an error message when equality—in consideration of usual converter tolerances—no longer exists. However, as an A/D converter is relatively costly to purchase, in particular when high demands are placed on its speed and accuracy, this solution is generally considered disadvantageous for cost reasons.
Therefore, an object of the present invention is to provide a circuit configuration with an A/D converter wherein monitoring of the function of the A/D converter, which is necessary for safety-critical applications, is possible with a reduced effort and structure in circuitry.
This object is achieved by the present invention wherein a ramp signal generator for generating a ramp voltage that is delivered to the input of the A/D converter, and a test circuit for activating a test cycle which comprises a first run of the ramp, by which a reference measurement of the ramp signal generator is carried out for compensating component tolerances, and a second run of the ramp where an error message is output when the value that is calculated for a transmission characteristic of the A/D converter lies outside a predetermined tolerance range of the measured value of the transmission characteristic.
A special advantage of this solution is that due to the reference measurement in the first run and the thus possible compensation of various tolerances of the ramp signal generator the circuit complexity of the latter can be kept within relatively close limits.
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“An on chip ADC test structure”; Yun-Che Wen; Kuen-Jong Lee; Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings , 2000; pp. 221-225.*
Henkel, W.; “Bestimmung der Linearität von A/D-Umsetzern”; Elektronik; vol. 15 (1984) p. 85-86.
Fey Wolfgang
Oehler Peter
Continential Teves AG & Co. oHG
Nguyen Khai M.
Rader & Fishman & Grauer, PLLC
Tokar Michael
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