Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-13
2003-08-19
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200
Reexamination Certificate
active
06608777
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration for reading memory cells of memory elements and/or for measuring or calibrating current of components in memory elements. In particular, the invention relates to the field of EPROM or EEPROM elements.
In the art of memory elements, erasable programmable ROM memories such as EPROMs (Erasable Programmable ROMs) and EEPROMs (Electrically Erasable Programmable ROMs) have existed for a long time. In these ROMs, the programmable elements are formed by MOS transistors with a floating, i.e., electrically insulated, polysilicon gate, which is charged by the tunnel current flowing through a thin oxide layer given high field intensities. In the programming operation, a relatively high gate voltage is applied, whereas in the read operation a lower read voltage, which is merely above the threshold voltage of the MOS transistor, is applied. In the EEPROM memory elements that are customarily used, the read voltage is typically 2.4 V. The memory contents of the EEPROM cells are read by evaluating the current, i.e., the transistor current that flows given an applied gate voltage of 2.4 V is evaluated. Such is accomplished by feeding the transistor current to the positive input of a current comparator while feeding a reference current to the negative input. In these types of memory structures, whose cells are evaluated by current evaluation, reference current sources are required accordingly.
An external access to the overall system is usually required for determining and calibrating the current-sensitive components, i.e., primarily the reference cell field serving as the reference current source. The access is provided by connecting particular internal lines such as bit lines or reference lines to external pads with switches in the form of transmission gates. The measuring of currents in the overall system is then accomplished using external current measuring devices or indirectly using voltage measuring devices and a previously determined conversion factor. The disadvantage of such a technique is that, in the case of closed systems such as chip cards, it is impossible to implement the described form and manner of external access.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for reading memory elements and for measuring or calibrating the current of components in memory elements, particularly EPROM or EEPROM memory elements, that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and with which it is possible to measure or calibrate the current in a simple and universally applicable and efficient fashion regardless of the system configuration, i.e., the utilization of a closed or open system. In particular, the invention makes possible to measure or calibrate current for closed systems such as chip cards in a simple fashion. Preferably, the components are in EPROM or EEPROM memory elements.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a circuit configuration for one of measuring and calibrating current of components in memory elements, including a memory cell field, a reference cell field, a current comparator having first and second inputs, a digital-analog converter receiving a digital signal having digital values and outputting predetermined current values based upon receiving corresponding ones of the digital values, a first switch having an output connected to the first input of the current comparator, a first input connected to the memory cell field, and a second input connected to the reference cell field; and a second switch having an output connected to the second input of the current comparator, a first input connected to the reference cell field, and a second input connected to the digital-analog converter.
An essential idea of the invention is found in utilizing a digital-analog converter that is connected in a specific fashion to the components on the memory element, i.e., the memory cell field, the reference cell field constituting a reference current source, and the current comparator. The digital-analog converter is configured for setting a plurality of prescribed current values upon the inputting of corresponding digital values.
The inventive circuit configuration makes possible a solution for determining the precise cell current in an optimal test time without additional external measuring devices and is, thus, especially well suited to closed systems such as chip cards. The described circuit configuration additionally makes possible a precise object programming of memory cells without an external reference current and also can be utilized in closed systems such as chip cards in this respect.
However, if so desired, in accordance with a concomitant feature of the invention, the second switch includes a third input for connecting an external current source. Such an option should be used primarily or exclusively in open systems but not in closed systems, such as chip cards. When used in open systems, the option optimizes the test time.
The circuit configuration according to the invention enables the precise determination of memory cell and reference cell currents on chip without external measuring devices with the aid of the digital-analog converter that is integrated into the circuit configuration. In a memory element such as an EPROM or EEPROM memory, the circuit configuration according to the invention is disposed on a common substrate with the memory cell field, the reference cell field constituting the reference current source, and the current comparator.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for reading memory elements, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 5444656 (1995-08-01), Bauer et al.
patent: 5835412 (1998-11-01), Tran
patent: 5973959 (1999-10-01), Gerna et al.
Bloch Martin
Thalmaier Carmen
Greenberg Lawrence A.
Ho Hoai
Infineon - Technologies AG
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