Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Patent
1999-07-26
2000-10-10
Cunningham, Terry D.
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
327537, G05F 302
Patent
active
06130574&
ABSTRACT:
A circuit configuration for producing negative voltages includes a first transistor having a first connection connected to an input connection, a second connection connected to an output connection of the circuit configuration and a gate connection connected through a first capacitor to a first clock signal connection. A second transistor has a first connection connected to the gate connection of the first transistor, a second connection connected to the second connection of the first transistor and a gate connection connected to the first connection of the first transistor. A second capacitor has a first connection connected to the second connection of the first transistor and a second connection connected to a second clock signal connection. The transistors are MOS transistors produced in a triple well. A third transistor has a first connection connected to the second connection of the first transistor, a second connection connected to the well(s) containing the transistors and a gate connection connected to the first connection of the first transistor. A charge pump having at least two of the circuit configurations and a method of operating the charge pump are also provided.
REFERENCES:
patent: 5335200 (1994-08-01), Coffman et al.
patent: 5422586 (1995-06-01), Tedrow et al.
patent: 5489870 (1996-02-01), Arakawa
patent: 5589793 (1996-12-01), Kassapian
patent: 5612921 (1997-03-01), Chang et al.
patent: 5625544 (1997-04-01), Kowhik et al.
patent: 5767733 (1998-06-01), Grugett
patent: 5818758 (1998-10-01), Wojciechowski
patent: 5821805 (1998-10-01), Jinbo
"A 5-V-Only Operation 0.6-.mu.m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure" (Umezawa et al.), 8107 IEEE Journal of Solid-State Circuits 27, No. 11, Nov. 1992.
Bloch Martin
Lauterbach Christl
Cunningham Terry D.
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
LandOfFree
Circuit configuration for producing negative voltages, charge pu does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit configuration for producing negative voltages, charge pu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit configuration for producing negative voltages, charge pu will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2259768