Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Lumped type parameters
Reexamination Certificate
2001-01-16
2002-12-31
Le, N. (Department: 2858)
Electricity: measuring and testing
Impedance, admittance or other quantities representative of...
Lumped type parameters
Reexamination Certificate
active
06501283
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a circuit configuration for measuring the capacitance of structures in an integrated circuit having a test structure and a reference structure. The circuit configuration includes first and second series circuits having transistors with controlled paths connected in series. The transistors of the series circuits are connected in parallel between supply terminals each supplying one supply potential. A terminal for the test structure is connected to a coupling node of the transistors of the first series circuit. A terminal for the reference structure is connected to a coupling node of the transistors of the second series circuit.
Integrated circuits have a structural, topographic construction, which is generally disposed in layers. For example, the integrated circuit has transistors and metal conductor tracks which are applied in layers one beside another or one above another on a semiconductor substrate. Modern integrated semiconductor circuits almost always have relatively small structure sizes and are operated with increasingly rising clock rates. The influence of capacitances on the signal speed generally increases with increasing transmission rates. Such capacitances can occur, for example, between the layers of metal conductor tracks and/or contact-making areas of transistors. In the course of the continued development of an integrated circuit, the aim is therefore to determine various types of capacitances and to influence them in a desired way.
Capacitances are determined, for example, by using large test structures. In addition, capacitances in integrated circuits can be determined through the use of the so-called charge-based capacitance measurement (CBCM) technique. That technique is described, for example, in a publication entitled “Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitance Measurement (CBCM) Technique and Three-Dimensional Simulation”, by D. Sylvester, J. C. Chen and C. Hu, in IEEE J. Solid State Circuits, 33 (1998). The method described therein is applied in particular to the determination of different types of capacitances on metal conductor tracks in an integrated circuit. A measurement circuit having two transistor series circuits which are each connected to a test structure and, respectively, a reference structure, is also presented. Through the use of that circuit, relatively small structures or small capacitances in integrated circuits can in particular advantageously be determined. That is because, by including a reference structure, parasitic capacitances, for example on feed lines, can be compensated for in particular. In so doing it circumvents the metrological problem that, as a result of smaller and smaller values of the capacitances to be measured, corresponding calibration of measuring instruments is generally no longer sufficient to eliminate measurement errors.
The function of the circuit which is described resides in particular in that the test structure associated with a specific capacitance, and the reference structure placed in a relationship thereto, in each case have their charge reversed between two potentials. In that device, in each case the average charge reversal currents are measured and their difference is used to determine the capacitance to be determined.
Different types of capacitances generally occur at contacted areas of a transistor in an integrated circuit. They can, for example, be a so-called junction capacitance, a capacitance between source/drain regions and a substrate, a so-called thin layer capacitance, a capacitance between a gate region and the substrate, and a so-called overlap capacitance, a capacitance between the gate region and the respective source/drain region. Those capacitances generally depend on the respective potential value being applied. That means that those capacitances are voltage-dependent and therefore have to be determined in a voltage-dependent, differential capacitance measurement. Since, in the circuit described, the capacitances have their charges reversed between a fixed reference potential of the integrated circuit and a positive potential, voltage-dependent capacitance measurement is only possible to a restricted extent.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for measuring the capacitance of structures in an integrated circuit, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and with which a voltage-dependent, differential capacitance measurement is possible.
The reference structure has a construction which is essentially similar to the test structure. The construction may be of the layer type, for example when measuring capacitances at the terminals of a transistor disposed in layers. It is also possible to measure so-called lateral wire-wire capacitances in the test structure, using an appropriately similarly constructed reference structure which, in this case, contains only the wiring which is essential for the measurement.
With the foregoing and other objects in view there is provided, in accordance with the invention, in an integrated circuit having a test structure with a terminal and a reference structure with a terminal, a circuit configuration for measuring a capacitance of structures. The circuit configuration comprises supply terminals each supplying a respective supply potential. A controllable voltage source is connected to the supply terminals. First and second series circuits each have two transistors with controlled paths connected in series. The transistors of the first and second series circuits are connected in parallel between the supply terminals. A first coupling node is connected to the terminal for the test structure and is connected to the transistors of the first series circuit. A second coupling node is connected to the terminal for the reference structure and is connected to the transistors of the second series circuit.
A voltage-dependent, differential capacitance measurement can be carried out by connecting the supply terminals of the two series circuits to the controllable voltage source.
For example, the supply voltages are set by the voltage source in such a way that the result is a relative potential difference of 0.1 V, for example. The level of the supply voltages can be varied in discrete steps between the measurements. In this way, different working points are established on the capacitances to be measured, which means that a differential capacitance measurement can be carried out.
In accordance with another feature of the invention, in each case PMOS transistors are used for charging each of the test structure and the reference structure, and NMOS transistors are used for discharging the test and reference structures. When the supply voltage falls, there is the risk that the gate voltage which is present will rise above the threshold voltage of the PMOS transistor. Lowering the gate voltage in this regard to negative values in order to avoid potential shifts on the entire integrated circuit is generally not suitable. NMOS transistors are provided in the circuit configuration according to the invention to ensure complete charging of the test and reference structures, even at potential values which are close to the reference potential of the integrated circuit. The gate connections of the respective NMOS transistors can be controlled by a positive potential in such a way that the respective transistor is located in the low-resistance range, even at a low supply potential.
In accordance with a concomitant feature of the invention, in a similar way, the circuit configuration for setting working points with a negative potential value has NMOS transistors each having an insulated p-doped trough. The insulated trough, which is located in a likewise p-doped substrate, in this case is connected to a corresponding negative potential.
Other features which are considered as characteristic for the invention are set
Lindolf Jürgen
Schatt Stefanie
Greenberg Laurence A.
Infineon - Technologies AG
Kerveros James
Mayback Gregory L.
Stemer Werner H.
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