Circuit configuration for generating logical butterfly structure

Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Comparing counts

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377 55, 377 56, 307463, H03K 2102, H03K 2108, H03M 1300

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active

053094948

ABSTRACT:
A circuit configuration includes k linking cells each generating one of k output states from two of k input states. Each of the linking cells have two counters. Each of the counters have a serial data input, a serial data output, and a serial counting width input. The counters increase a counter state loaded through the data input and represent the respectively assigned input state by a value input through the counting width input. Comparators are each connected to the data outputs of two of the counters for serially comparing the two counter states with one another. Multiplexers are each connected to the data outputs of two of the counters for outputting one of the two counter states as an output state under the control of the comparator. Each two further multiplexers are connected upstream of the respective counters and are switched through for loading the counter states with the respectively assigned input states and for comparing the counter states at the data outputs with the counter states at the data inputs of the respective counters.

REFERENCES:
patent: 2949228 (1960-08-01), Bailey et al.
patent: 3134091 (1964-05-01), Shugart
patent: 3265867 (1966-08-01), Venn et al.
IEEE Custom Integrated Circuits Conference, 1987, J. Stahl & A. Meyr: "A Bit Serial Viterbi Decoder Chip for the MBIT/S Range", pp. 551-554.

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