Electrical pulse counters – pulse dividers – or shift registers: c – Starting – stopping – presetting or resetting the counter – Counter chains with a radix or base other than the number...
Patent
1994-12-01
1996-06-04
Heyman, John S.
Electrical pulse counters, pulse dividers, or shift registers: c
Starting, stopping, presetting or resetting the counter
Counter chains with a radix or base other than the number...
377 48, 377104, 327176, H03K 2366
Patent
active
055240372
ABSTRACT:
A circuit configuration generates an even-numbered duty factor with an odd-numbered division n of a symmetrical clock signal. A first device generates a first output signal from the symmetrical clock signal. The first output signal begins upon each n.sup.th edge of one type, of a symmetrical clock signal and remains active for a length of N-1/2 periods of the symmetrical clock signal. A second device generates a second output signal from the symmetrical clock signal. The second output signal begins upon each n.sup.th edge of another type, of the symmetrical clock signal and remains active for the length of N-1/2 periods of the symmetrical clock signal. A logic linkage is connected to the first and second devices for linking the two output signals to form one symmetrical output signal.
REFERENCES:
patent: 3902125 (1975-08-01), Oliva
patent: 4606059 (1986-08-01), Oida
patent: 4703495 (1987-10-01), Bereznak
patent: 4845727 (1989-07-01), Murry
patent: 5077764 (1991-12-01), Yamashita
Publication: Electronic World+Wireless World, Aug. 1990, p. 685 (Mark Watson) "Divide-by three with 1:1 M/S ratio".
Donig Gunter
Goetz Edmund
Herrmann Helmut
Greenberg Laurence A.
Heyman John S.
Lerner Herbert L.
Siemens Aktiengesellschaft
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