Circuit configuration for generating combinatorial binary logic

Details Circuit configuration for generating combinatorial binary logic Circuit configuration for generating combinatorial binary logic

1990-09-21

1992-01-07

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307445, 307465, 307243, H03K 1902, H03K 19173

Patent

active

050794469

ABSTRACT:
A circuit configuration for generating combinatorial logic functions includes a plurality of cascading circuit blocks, which are each formed of a 1-out-of-4 multiplexer and an inverter. Control inputs of the multiplexer are acted upon by input variables having a higher significance and data inputs are acted upon by a logical zero, a logical one, least significant input variables or inverted least significant input variables, in dependence on a linking function.

REFERENCES:
patent: 4366393 (1982-12-01), Kasuya
patent: 4670846 (1987-06-01), Laws
patent: 4818902 (1989-04-01), Brockmann
patent: 4825105 (1989-04-01), Holzle
patent: 4866310 (1989-09-01), Ando et al.
Publication Electronics International, vol. 50, No. 9, Apr. 1977, pp. 120-121, New York, U.S.; J. E. Siebert: "Digital multiplexers reduce chip count in logic design".

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