Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-01-31
2002-04-02
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230020, C365S194000
Reexamination Certificate
active
06366527
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration for generating a local output clock signal for controlling an instant at which data are output from an output delay device at an output of a cell array of a memory onto a data highway. The local output clock signal can be generated using a clock ratio compensator and a multiplexer in a manner dependent on a differential input clock signal and a programmable switch-over signal, in such a way that the outputting of the data onto the data highway is synchronized with either whole clock cycles of the data highway or else integer fractions thereof.
Memory chips generally contain a plurality of cell arrays or cell array strips in which the data are stored, the cell arrays are connected to inputs/outputs of the memory chip by a plurality of control devices and data highways.
In order to coordinate the data stream produced during data accesses to the cell arrays, a clock signal is used. This signal, once it has been passed to a signal input of a cell array, drives across the entire cell array and ensures that the data situated in the activated memory cells are read and brought to the output of the cell array, from where they pass onto the data highway.
In double data rate synchronous dynamic random access memory chips (double data rate memory chips with synchronous access), DDR SDRAMs for short, a differential input clock signal is used as the clock signal. It contains two clock pulses of the same frequency which are shifted by half a clock cycle relative to one another.
In order to avoid data collisions, the data which have been brought to the output of the cell array must be output onto the data highway at a precisely defined output instant, which must be synchronized with the clock of the data highway. In this case, the outputting of the data onto the data highway may be synchronized with either whole clock cycles of the data highway or else integer fractions thereof. Since the individual data that are intended to be accessed are stored at different locations within the cell array, it is possible for the individual data to arrive in the “wrong” order, too early or too late at the output of the cell array. Therefore, particularly in the case of DDR SDRAMs, it is customary to provide at the output of a cell array an output delay device which ensures that the arriving data are sorted correctly and output onto the data highway at a precisely defined instant. By way of example, the output delay device is realized by a shift register, known per se.
In order to control the data output by the output delay device, a highly precise output clock signal, inter alia, is required, which is newly generated by the two clock pulses of the differential input clock signal locally in the output delay device. This output clock signal must have a clock ratio of almost 50%. The differential input clock signal itself is unsuitable for this task since the falling edges of the differential clock pulse, as a result of being driven across the cell array, “smear”, that is to say lose definition and thus timing force.
The generation of the output clock signal is normally achieved by only one type of edges of the differential input clock signal, for example the rising edges, which are not subject to the problem of “smearing” and thus yield a usable measure of both whole and, for example, half clock cycles, being applied to a clock ratio compensator. The latter generates, from the two rising edges of the two clock signals of the differential input clock signal, an output clock signal which contains two clock signals and, on account of sharp rising edges and of sharp falling edges, has a “maximum” clock ratio, i.e. the pulses of the two clock signals are maximally wide but do not overlap one another.
In order that the above-described output delay device can be used as flexibly as possible, the output clock signal which controls the output delay device and is generated by the clock ratio compensator can additionally be altered by a programmable switch-over signal over the period of any desired clock cycles. The switch-over signal thus influences the clock rate of the output clock signal and, moreover, determines at which of the possible output instants the corresponding data (bits) are output. The possible output instants themselves are determined, as described above, by the differential input clock signal.
The output clock signal “cleaned up” by the clock ratio compensator is altered for example by a multiplexer which is connected downstream and arbitrarily interchanges the signal levels of the two clock signals of the output clock signal in a manner dependent on the programmable switch-over signal.
What is disadvantageous about the prior art described above is that despite clock ratio compensators, on account of signal propagation time differences within the clock ratio compensation, the two “cleaned up” clock signals at the output of the clock ratio compensator are not absolutely exactly inverted with respect to one another but rather are additionally shifted by a small amount relative to one another, which produces a signal overlap and can thus lead to problems during the data output. Furthermore, the series connection of the clock ratio compensator and the multiplexer has the effect that a relatively long time passes before the “completion” of the output clock signal, which can lead to synchronization problems with the clock of the data highway and thus limits the maximum clock frequency of the memory.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for generating an output clock signal with optimized signal generation time which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which eliminates the disadvantages dictated by propagation time.
With the foregoing and other objects in view there is provided, in accordance with the invention, a combination of a memory chip with a circuit configuration for generating a local output clock signal for controlling an instant at which data are output from an output delay device at an output of a cell array of the memory chip onto a data highway. The circuit configuration contains outputs and a clock ratio compensator formed of two coupled, mutually symmetrical paths for generating the local output clock signal and receiving a differential input clock signal. Each of the two coupled, mutually symmetrical paths have switches connected to one of the outputs, and a multiplexer formed of at least two programmable signal feed-in points connected to the switches. The multiplexer provides the local output clock signal in a manner dependent on a switch-over signal and is connected through the switches to one of the outputs. The switches are opened and closed in a manner dependent on the differential input clock signal, and an outputting of the data onto the data highway is synchronized with whole clock cycles of the data highway or integer fractions of the whole clock cycles.
The object is achieved according to the invention by virtue of the fact that the clock ratio compensator is constructed from two coupled, mutually symmetrical paths in which the multiplexer is integrated and has in each case at least two programmable signal feed-in points, which generate the output clock signal in a manner dependent on the switch-over signal and are connected via switches to the outputs of the circuit configuration. The switches being opened or closed in a manner dependent on the differential input clock signal.
The clock ratio compensator is constructed from the two mutually symmetrical paths. Each of the two inputs of the circuit configuration is connected to one of the two paths.
Each of the paths has an operating cycle that is repeated periodically and can be divided into two phases: an output clock signal preparation phase and an output clock signal output phase. The operating phases of the two paths are complementary to one another, i.e. while one path is in the output clock signal prepara
Hein Thomas
Heyne Patrick
Marx Thilo
Partsch Torsten
Greenberg Laurence A.
Hoang Huan
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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