Circuit configuration for generating an enable signal for a cloc

Details Circuit configuration for generating an enable signal for a cloc Circuit configuration for generating an enable signal for a cloc

1996-09-19

1998-04-14

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327142, 327160, 327198, H03K 1722

Patent

active

057397082

ABSTRACT:
A circuit configuration for generating an enable signal for a clock-controlled circuit includes a device for generating a power-on reset signal. Deactivation of that signal is delayed through the use of a delay device, and is used for enabling a clock signal output by an oscillator. The circuit is controlled in clocked fashion through the use of the signal. A delay time of the delay device is controlled by the oscillator through a level weighting device, preferably a Schmitt trigger. As a result, the clock signal is not enabled until the oscillator is oscillating at stable amplitude and at a desired frequency.

REFERENCES:
patent: 4300065 (1981-11-01), Remedi et al.
patent: 5028824 (1991-07-01), Young
patent: 5231319 (1993-07-01), Crafts et al.
patent: 5343085 (1994-08-01), Fujimoro et al.
patent: 5376834 (1994-12-01), Carobolante
Patent Abstracts of Japan No. 59-156018 (Tachibana), dated Sep. 5, 1984.

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