Circuit configuration for generating a rest signal

Details Circuit configuration for generating a rest signal Circuit configuration for generating a rest signal

1992-01-29

1993-10-05

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072964, 3072965, 307594, G11C 1100, H03K 301

Patent

active

052508536

ABSTRACT:
A circuit configuration for generating a reset signal includes a bistable switch element assuming a preferential state upon application of a supply voltage. The bistable switch element has an output carrying a reset signal in the preferential state and has an input. An on and off switchable reference voltage source has a control input connected to the output of the bistable switch element. The on and off switchable reference voltage source is switched on in the preferential state of the bistable switch element. An on and off switchable delay line has a control terminal connected to the output of the bistable switch element, an output connected to the input of the bistable switch element, and a reference input connected to the on and off switchable reference voltage source for switching on the delay line in the preferential state of the bistable switch element. The bistable switch element is switched out of the preferential state with a time delay when the supply voltage exceeds a reference value specified by the on and off switchable reference voltage source.

REFERENCES:
patent: 3895239 (1975-07-01), Alaspa
patent: 4634904 (1987-01-01), Wong
patent: 4797584 (1989-01-01), Aguti et al.
patent: 4818904 (1989-04-01), Kobayashi
patent: 5039875 (1991-08-01), Chang
patent: 5115146 (1992-05-01), McClure
IEEE Journal of Solid-State Circuits, vol. SC-12, No. 5, Oct. 1977, New York, pp. 502-506; Stewart.

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