Circuit configuration for dividing a clock signal

Details Circuit configuration for dividing a clock signal Circuit configuration for dividing a clock signal

1995-05-17

1996-09-17

Wambach, Margaret Rose

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

377110, 377117, H03K 2366

Patent

active

055576494

ABSTRACT:
A circuit configuration being made by differential technology for dividing a clock signal with switchable divider ratios of 4/5 by emitter coupled logic, includes first, second and third series-connected flip-flops each having an output, a data input and a clock input. The output of the second flip-flop is coupled to the data input of the third flip-flop, and the clock inputs of the first, second and third flip-flops are acted upon by a clock signal. A first AND gate is connected upstream of the first flip-flop and has a first input being acted upon by a control signal for switching over the divider ratio, and a second input being acted upon by an inverted signal from the output of the third flip-flop. A second AND gate is connected between the first and second flip-flops and has an output connected to the data input of the second flip-flop, a first input receiving an inverted signal from the output of the first flip-flop, and a second input being acted upon by the inverted signal from the output of the third flip-flop.

REFERENCES:
patent: 4606059 (1986-08-01), Oida
patent: 4703495 (1987-10-01), Bereznak
patent: 5077764 (1991-12-01), Yamashita
patent: 5349622 (1994-09-01), Gorisse
Plessey Semiconductor Publ. No. SP8690/1A&B, pp. 113-117, High Speed Dividers Integrated Circuit Handbook.

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