Circuit configuration for discharging a capacitor which has...

Details Circuit configuration for discharging a capacitor which has... Circuit configuration for discharging a capacitor which has...

2002-08-15

2003-08-12

Tso, Edward H. (Department: 2838)

Electricity: battery or capacitor charging or discharging

Capacitor charging or discharging

Reexamination Certificate

active

06605927

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration for discharging a first capacitor which has been charged to a high voltage to a low voltage under the control of a control unit. One electrode of the first capacitor is thereby connected to reference-ground potential while the other electrode thereof is connected via the path electrodes of a first transistor to one electrode of a second capacitor whose other electrode is connected to reference-ground potential. A voltage source with its internal resistance is arranged in parallel with the second capacitor. Modern semiconductor circuits require a supply voltage which is both higher and lower than the supply voltage normally available. Semiconductor circuits containing memories such as flash, EEPROM, DRAM or FRAM require high voltages, whereas at the same time technologies in the order of magnitude of 0.25 &mgr;m to 0.18 &mgr;m require low supply voltages of, by way of example, 2.5 V, 1.8 V down to 1 V. Such low supply voltages are also necessary in order to keep the power consumption, particularly of contactless systems, such as mobile telephones, chip cards, smart cards, or devices in medical engineering, as low as possible.
FIG. 2
shows a prior art circuit configuration for discharging a first capacitor which has been charged to a high voltage to a low voltage under the control of a control unit, which is used in semiconductor circuits.
In the circuit of
FIG. 2
, one electrode of a first capacitor CH is connected to reference-ground potential while the other electrode thereof is connected to the source electrode of a PMOS field effect transistor P
1
. The drain electrode of the PMOS field effect transistor P
1
is connected via a capacitor CL to reference-ground potential. Connected in parallel with the capacitor CL is a voltage source UL with its internal resistance RL. The source electrode of the PMOS transistor P
1
is connected to reference-ground potential via a series circuit comprising the source-drain path of a PMOS transistor T
1
and that of a field effect transistor T
2
. Connected in parallel with the series circuit comprising the source-drain paths of the two transistors T
1
and T
2
is a series circuit comprising the source-drain path of a PMOS transistor T
3
and that of a field effect transistor T
4
. The gate electrode of the PMOS transistor T
1
is connected to the common node for the two transistors T
3
and T
4
and to the gate electrode of the PMOS transistor T
1
. The gate electrode of the PMOS field effect transistor T
3
is connected to the common node for the two transistors T
1
and T
2
. The gate electrode of the transistor T
4
is connected to the gate electrode of the transistor T
2
via an inverter IN. The output of a control unit SE is connected to the gate electrode of the transistor T
4
and hence to the input of the inverter IN.
The transistors T
1
to T
4
and the inverter IN represent a level converter.
The operation of the circuit configuration depicted in
FIG. 2
is as follows:
The capacitor CH has been charged to the high voltage VH. The output of the control unit SE outputs a logic zero to the level converter, which turns off the PMOS field effect transistor P
1
. If the control unit SE outputs a logic 1 to the level converter, the PMOS transistor P
1
turns on, so that the two capacitors CH and CL are connected in parallel. A discharge current I
1
then flows from the capacitor CH through the PMOS field effect transistor P
1
to the capacitor CL. This discharging operation proceeds according to a 1/e
t
function, which means that, theoretically, the voltage across the capacitor CH falls to the voltage VL across the capacitor CL as t→∞. For this reason, the discharging operation takes a relatively long time. On account of the fact that the voltage source UL is not an ideal voltage source but rather a real voltage source, the voltage across the capacitor CL will be above the voltage VL by a small value and will not fall to the voltage value of the voltage source UL until toward the end of the discharging operation. On account of the fact that the potential on the gate electrode of the PMOS transistor P
1
is quickly discharged to ground, this transistor P
1
is subject to a high level of wear which considerably reduces its useful life and its reliability.
In order for the capacitor CH to be discharged to the voltage VL as accurately as possible, the capacitor CL needs to be chosen to be as large as possible, while the internal resistance RL of the voltage source UL needs to be chosen to be as small as possible. This requires precise knowledge of the characteristic curves for the capacitor CH and for the conduction resistance of the PMOS transistor P
1
. The greater the internal resistance RL of the voltage source UL, the larger the capacitor CL needing to be chosen to compensate. Following the discharging operation, the voltage VL across the capacitor CL can still be high enough for downstream circuit configurations with CMOS field effect transistors to be destroyed. This is the case, for example, when a supply voltage of 16 V is required for an EEPROM and a supply voltage of 1.5 V is required for a CMOS circuit configuration.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for discharging a first capacitor from a high voltage to a low voltage under the control of a control unit which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which attains a rapid discharge to precisely the low voltage that is required.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration, comprising:
a first capacitor having a first electrode connected to reference-ground potential and a second electrode;
a second capacitor having a first electrode connected to reference-ground potential and a second electrode;
a first field effect transistor having a source electrode and a drain electrode connected between the second electrode of the first capacitor and the second electrode of the second capacitor;
a voltage source having an internal resistance connected in parallel with the second capacitor;
a second field effect transistor and a third field effect transistor connected to form a series circuit;
a first common node between the source electrode of the first field effect transistor and the first capacitor connected to reference-ground potential via the series circuit formed of the second field effect transistor and the third field effect transistor;
a fourth field effect transistor and a fifth field effect transistor connected to form a series circuit;
a second common node between the drain electrode of the first field effect transistor, the second capacitor, and the voltage source connected to reference-ground potential via the series circuit formed of the fourth field effect transistor and the fifth field effect transistor;
the first, fourth and fifth field effect transistors each having a gate electrode connected to a common node between the second and third field effect transistors);
a sixth field effect transistor having a gate electrode and having a path connected between reference-ground potential and a common node between the fourth and fifth field effect transistors, and the second field effect transistor having a gate electrode connected to the common node between the fourth and fifth field effect transistors;
an inverter having an input and having an output connected to the gate electrode of the sixth field effect transistor; and
a control unit having a control output connected to a gate electrode of the third field effect transistor and to the input of the inverter.
In accordance with an added feature of the invention, a protective resistor is connected between the third field effect transistor and reference-ground potential.
In accordance with an additional feature of the invention, the first, second and fourth field effect transistors are PMOS field

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