Circuit configuration for digital bit-serial signal processing

Details Circuit configuration for digital bit-serial signal processing Circuit configuration for digital bit-serial signal processing

1991-12-11

1993-04-20

Mai, Tan V.

Boots, shoes, and leggings

36472414, G06F 750, G06F 731

Patent

active

052048314

ABSTRACT:
A circuit configuration for digital bit-serial signal processing includes n input shift registers each being written in parallel or serially with an input data word and then read out by shifting to the right. Sign repetition devices are each assigned to a respective one of the input shift registers for continuously generating and shifting an algebraic sign of the input data word onward in the shift to the right. A serial arithmetic unit is connected downstream of the input shift registers for serially outputting output data words. m output shift registers connected downstream of the serial arithmetic unit are written in serially with the output data words and read out in parallel and/or serially. A control unit is connected to the serial arithmetic unit. Once all of the output data words have been fully written in the respective output shift registers, the control unit ends a readout of the input shift registers and the writing in of the output shift registers, for bringing the arithmetic unit to a defined initial state, and for enabling the input shift registers for writing in new input data words.

REFERENCES:
patent: 3941990 (1976-03-01), Rabasse
patent: 4285047 (1981-08-01), Ohnishi
patent: 4336600 (1982-06-01), Houdard et al.
patent: 4774686 (1988-09-01), McClary et al.
Motorola, AN-286, Appl. Note Integrated Circuits, Renschler et al: "Binary Addition Using MRTL Integrated Circuits", 1967, USA.

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