Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-08-08
2002-11-05
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230010
Reexamination Certificate
active
06477106
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration for deactivating word lines in a memory matrix. Each of the word lines is connected to a controllable connection device for connecting the relevant word line to a common supply line system carrying a deactivation potential for the word line. A control circuit which in response to the deactivation command, produces a deactivation control signal that turns on the controllable connection device.
In normal digital information memories, the memory cells form a matrix of rows and columns. To select a memory cell for the purposes of writing or reading, a word line associated with the relevant row is activated and a bit line associated with the relevant column is driven. The selected activation of the word lines, that is to say the “addressing” of the rows in the matrix, is normally performed by a row address decoder which has outputs individually connected to the word lines and inputs for receiving the bits of a digital row address.
Similarly, the selective driving of the bit lines is performed by a column address decoder.
A word line is activated by applying an activation potential which conditions the switching transistors of the associated memory cells such that the charges stored in the memory cells are transferred to the respective bit lines. The activation potential is applied by the row address decoder that selects the respective word line to be activated.
Once the read or write operation has been performed, the word line is deactivated again by bringing it to a deactivation potential which turns off the cell transistors. The deactivation potential is applied by the row address decoder by turning on a connection device that is individually associated with the relevant word line and connects the relevant word line to a supply line system carrying the potential relating thereto. The connection device is normally a transistor switch that is turned on fully in response to a deactivation command.
In some tests carried out on memory matrices for the purposes of a checking operation, word lines are temporarily activated and subsequently deactivated without performing a write or read operation during activation. The test activation can be used, for example, to detect a risk of leakage currents, in particular when, in this context, the activation is maintained over a relatively long period and/or is carried out using a slightly increased activation potential. Such leakage currents can flow, by way of example, from the activated word lines to memory cells on adjacent unactivated word lines. Any leakage currents arising therefore influence the charge state of memory cells on unactivated word lines, which can be established by subsequently checked the memory contents thereof. To save test time, the test activation is preferably carried out on a plurality of word lines at the same time, specifically using such a selection that the activated word lines have unactivated exemplars adjacent to them. This “multiple word line select”, which can be preprogrammed in the row address decoder, should, by way of example, contain the selection of each fourth word line for activation, while the word lines situated in between are kept inactive.
When a plurality of active word lines are deactivated at the same time, the discharge currents flowing via the associated deactivation transistors add up to form a relatively high total current which burdens the network carrying the deactivation potential. In this context, the network primarily contains the inactive word lines and wiring in the row address decoder, which wiring is relatively narrow for space reasons, and thus has a relatively high resistance, and also distributes the deactivation potential to associated connections of other elements of the decoder. As a result of the high resistance of the metallized area forming the wiring, the simultaneous deactivation of the active word lines produces a resistive voltage drop across the network, which voltage drop burdens the other, inactive word lines, most severely the directly adjacent exemplars. In this case, a relatively large voltage elevation occurs which is proportional to the number of active word lines and is thus proportional to the time saving aimed for. The voltage elevation that occurs causes a reduction in the blocking effect of the associated cell transistors in the affected word lines, and this can erase some or all of the information in connected cells.
To prevent this risk, the number of word lines which are respectively selected at the same time for the multiple word line select has been kept down to date. In consequence, however, a longer test time was needed. One alternative would be to configure the deactivation potential network to have a very low resistance, but this would require wider metallized areas and is undesirable for space reasons.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for deactivating word lines in a memory matrix that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which permit even a relatively large number of active word lines on a memory matrix to be deactivated at the same time and without perturbing accompanying effects.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for deactivating word lines in a memory matrix of a memory. The circuit configuration contains a common supply line system carrying a deactivation potential for the word lines, and controllable connection devices connected to the common supply line and to be connected to the word lines. The controllable connecting devices connect each of the word lines to the common supply line system carrying the deactivation potential for the word lines. A control circuit is provided and has an output connected to the controllable connection devices. The control circuit receives a deactivation command and in response to the deactivation command produces a deactivation control signal available at the output. The deactivation control signal turns on the controllable connection devices resulting in turned-on controllable connection devices. The control circuit has a reduction device connected to the output and the reduction device can be switched on selectively and which, when switched on, limits currents flowing through the turned-on controllable connection devices to such an extent that a total current flowing through the common supply line system does not exceed a prescribed value.
Accordingly, the invention is implemented on a circuit configuration for deactivating the word lines in the memory matrix. Each of which has the controllable connection device for connecting the relevant word line to the common supply line system carrying the deactivation potential for the word lines. The control circuit is provided which, in response to a deactivation command, produces a deactivation control signal that turns on the controllable connection devices. According to the invention, the control circuit contains a reduction device which can be switched on selectively and which, when switched on, limits the currents flowing through the turned-on connection devices to such an extent that the total current flowing via the supply line system does not exceed a prescribed value.
The inventively provided reduction device permits large currents in the supply line system carrying the deactivation potential, and hence the aforementioned voltage elevations normally to be dreaded when the word lines are deactivated at the same time, to be reduced or prevented entirely. It is thus possible to carry out tests in the multiple word line select using far more word lines than previously, and thus to shorten the total test time on the memory matrix.
The desired current limiting can be achieved by changing the ratio of the effective resistances of the word line connection device and the deactivation potential supply line system. By increasing the size of the resistance of th
Fischer Helmut
Schnabel Joachim
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen Viet Q.
Stemer Werner H.
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