Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
1998-09-21
2001-02-13
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C327S202000, C327S203000, C327S212000
Reexamination Certificate
active
06188636
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration for storing data, in which the data are written in and read out under clock control.
For storing data in the form of logic signals, particularly for brief buffer storage, it is well known to use registers. A register maintains its logic state until it is changed by a different logic signal or by special control commands.
The storage of the data can be done dynamically, for instance by changing the load state of a capacitor, or statically, for instance with a bistable multivibrator.
The transfer of data from the register is done usually at fixed times that are determined by a clock signal. The output of the register is released only in certain clock phases, for instance at a leading or trailing edge thereof. Complete decoupling of the input from the output of the register is obtained if the transfer of data to the register is also possible only at certain times fixed by the clock signal, and if the data transfer and entry take place at different times. The decoupling assures that a datum is not overwritten by a subsequent datum before it is read out. In principle, such a register includes a unit for storing a datum in memory, a clocked switch for transferring the data to the unit, and a clocked switch for takeover of the data from a precursor stage. At any time, the switches must assume different circuit states from one another. If one switch is opened, the other must be closed, and vice versa.
Relaying data from the input to the output of the register is made up of a transfer step, in which the data are transferred to the circuit, and a takeover step, in which the data are taken over by the circuit.
A disadvantage here is that a datum at the input of the register is not available at the output until after a period length. To store the data in memory without loss, the clock frequency of the clock signal must be twice as high as the frequency with which the data at the input of the register can change their state. In other words, changes in the state of the data can occur at only half the frequency of the clock signal.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration for data storage which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type, in which a more-effective clock-controlled storage of data is provided.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration, including: an input terminal; an output terminal; a first memory device for storing data connected between the input terminal and the output terminal; first means connected in series with the first memory device, the first means receiving a clock signal for disconnecting the input terminal from the output terminal; a second memory device; second means connected in series with the second memory device, the second memory device and the second means connected in parallel with the first memory device and the first means, the second means being clocked in a push-pull fashion with the first means.
The invention has the advantage that the frequency with which the data can change their contents is equal to the frequency of the clock signal. In the circuit configuration of the invention, input data are stored at each trailing edge and each leading edge of a clock signal.
It is also advantageous that the power consumption per storage cycle is virtually unchanged compared with known circuit configuration for data storage.
In accordance with an added feature of the invention, the first means have a first MOS transistor of a first conductivity type is disposed upstream of the first memory device and a second MOS transistor of a second conductivity type is disposed downstream of the first memory device, and the second means have a first MOS transistor of the second conductivity type is disposed upstream of the second memory device and a second MOS transistor of the first conductivity type is disposed downstream of the second memory device.
In accordance with another feature of the invention, at least one of the first memory device and the second memory device has a pair of anti-parallel-connected inverters.
In accordance with an additional feature of the invention, at least one of the first memory device and the second memory device has an output terminal and a storage capacitor connected between the output terminal and a reference potential.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for data storage, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 4629909 (1986-12-01), Cameron
patent: 4744061 (1988-05-01), Takemae et al.
patent: 4802127 (1989-01-01), Akaogi et al.
patent: 5132577 (1992-07-01), Ward
patent: 5867446 (1999-02-01), Konishi et al.
Elms Richard
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Nguyen Hien
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