Circuit configuration for converting TTL-level signals into CML

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307446, 307455, 307448, H03K 19092, H03K 19094, H03K 19086, H03K 1901

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active

051051060

ABSTRACT:
A circuit configuration includes first, second and third current impressing devices. First and second bipolar transistors have coupled emitter terminals being connected through the first current impressing device to a first potential, collector terminals carrying output signals and being connected directly or through respective resistors to a second potential, and base terminals. A first field effect transistor has a gate terminal being acted upon by a first input signal, a drain terminal being connected through a further resistor to the second potential, and a source terminal being connected to the base terminal of the first bipolar transistor and through the second current impressing device to the first potential. A second field effect transistor has a gate terminal being acted upon by a reference potential, a drain terminal being connected through another resistor to the second potential, and a source terminal being connected to the base terminal of the second bipolar transistor and through the third current impressing device to the first potential.

REFERENCES:
patent: 4453095 (1984-06-01), Wrathall
patent: 4645951 (1987-02-01), Uragami
patent: 4943743 (1990-07-01), Pelley, III et al.
patent: 4994691 (1991-02-01), Naghshineh
patent: 5008570 (1991-04-01), Coddington
patent: 5013941 (1991-05-01), Jansson
Publication "The Integrated Circuits Catalog for Design Engineers", published by Texas Instruments in 1972, 3 pages.
IBM Technical Disclosure Bulletin, vol. 21, No. 7 Dec. 1978, Clemen et al: "V.sub.T -Compensated TTL-Compatible MOS Amplifier".

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