Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2002-04-02
2003-08-19
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230030, C365S230080, C365S145000
Reexamination Certificate
active
06608796
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a circuit configuration for controlling the word lines of a memory matrix. The invention is preferably used for dynamic random access memory devices (DRAMs) but is not limited to DRAMs and may advantageously be used for other types of memory devices.
In customary digital information memories, the memory cells form a matrix of rows and columns. In order to select a memory cell for reading from or writing to, a “word line” assigned to the relevant row is activated and a “bit line” assigned to the relevant column is addressed. A word line is activated by the application of an activation potential which conditions the assigned memory cells in such a way that they can be accessed via the bit lines in order to read or write memory information. After the reading or writing operation has been effected on the row, the relevant word line is deactivated again by being brought to a deactivation potential which cancels the aforementioned conditioning of the memory cells again.
For optional activation and deactivation, an assigned driver is connected to each word line. The respective driver and hence the relevant word line is selected through the use of a row address decoder which receives the bits of a digital row address. Each driver is, in principle, a switching device which, depending on control signals, establishes a low-impedance connection between the relevant word line and either a source of the activation potential or a source of the deactivation potential.
In the most customary cases, the drivers are provided at one of the column-parallel edges of the memory matrix and are connected to the “inputs” of the word lines that are situated there. If a signal is fed in at this location, then it propagates with a certain propagation speed along the line since the line behaves like an RC delay chain, principally on account of the distributed transverse capacitance in conjunction with the longitudinal resistance. After a changeover of the potential at the line input, with increasing distance from the input it thus takes increasingly longer until other locations on the line reach the full amplitude of the new potential.
This propagation time limits the maximum possible operating speed of the memory. In a customary operating mode, after a write or read cycle, the deactivation potential is applied to the word lines and a next cycle is permitted to be begun only when the potential has been established over the entire length of the word lines, including the word line that was selected in the preceding cycle, and, accordingly, the concluding precharge can be effected via the relevant row. The interval to be complied with here (“row precharge time”, abbreviated to “TRP”) must thus comply with the signal propagation time from the input to the end of the word line. The aforementioned intervals governed by the propagation time become a problem particularly in the case of large memory matrices with correspondingly long word lines. Enlarging the driver circuits cannot afford a temporal advantage here.
A limitation of the operating speed by the signal propagation time on the word line can be combated in a known manner by providing and connecting each driver in the center of the respective word line, so that the propagation time to the most distant point on the word line is halved. A further known solution proposal is the so-called “segmented word line” concept which, in principle, utilizes an even finer subdivision of the word line length. However, both concepts significantly increase the chip area. This is because space is taken up not only by the transistors of the drivers themselves but also by their leads, which have to run at an appropriate distance from one another and from the elements and lines of the memory matrix. This is because the leads must include all those lines which both control the selection of the relevant driver and command the activation or deactivation to be performed by the respective drivers; added to them are the leads for the activation potential and the deactivation potential. All these leads each have to be led to the locations of the relevant drivers, partly as a bundle firstly in the row direction to the location of the drivers and then in the column direction along all the driver circuits.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration which overcomes the above-mentioned disadvantages and which implements at least the commanded deactivation of word lines of a memory matrix in an accelerated fashion.
With the foregoing and other objects in view there is provided, in accordance with the invention, in combination with a memory matrix having word lines and memory cells connected to the word lines, the word lines having respective input terminals and respective remote terminals provided remote from the input terminals, a circuit configuration for performing a selective changeover of the word lines between an activation potential enabling access to given ones of the memory cells connected to a given one of the word lines and a deactivation potential inhibiting access to the given ones of the memory cells, the circuit configuration including:
a plurality of selectively addressable drivers each connected to a respective one of the input terminals of a respectively assigned one of the word lines and each being controllable by an assigned selection signal and a deactivation signal in order to connect the respective one of the input terminals to the activation potential if the selection signal is in an active state and the deactivation signal is in an inactive state, and in order to connect the respective one of the input terminals to the deactivation potential when the deactivation signal becomes active;
a source for providing the deactivation potential;
a plurality of auxiliary circuits connected to respective ones of the word lines at at least a respective one of the remote terminals, the plurality of auxiliary circuits including respective deactivation auxiliary switches each of which, depending on an assigned auxiliary switching signal, selectively establishes and inhibits a low-impedance conductive connection between a respective one the remote terminals and the source for providing the deactivation potential; and
a timing control circuit generating the respectively assigned auxiliary switching signal in a temporal relationship with the deactivation signal such that a corresponding one of the deactivation auxiliary switches is turned off while a corresponding one of the selectively addressable drivers of an assigned one of the word lines connects a corresponding one of the input terminals to the activation potential, and is turned on again as soon as the corresponding one of the selectively addressable drivers connects the corresponding one of the input terminals to the deactivation potential as a result of the deactivation signal becoming active.
In other words, the invention is realized in a circuit configuration for the selective changeover of the word lines of a memory matrix between an activation potential, which enables access to memory cells connected to the relevant word line, and a deactivation potential, which inhibits access to the memory cells, having a plurality of selectively addressable drivers, each of which is connected to an input terminal of a respectively assigned specimen of the word lines and can be controlled under the influence of an assigned selection signal and of a deactivation signal in order to put the relevant input terminal at the activation potential if the selection signal (AS) is in the active state and the deactivation signal is in the inactive state, and in order to put the relevant input terminal (
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) at the deactivation potential (L) when the deactivation signal becomes active. According to the invention, a respectively assigned auxiliary circuit is connected to each of the word lines at at least one terminal point remote from the input terminal, which auxiliary circuit contains a deactivation auxiliary s
Greenberg Laurence A.
Ho Hoai
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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