Circuit configuration for clock-controlled time division multipl

Details Circuit configuration for clock-controlled time division multipl Circuit configuration for clock-controlled time division multipl

1989-09-21

1992-09-08

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 581, H04J 116, H04J 314, H04Q 1104

Patent

active

051464535

ABSTRACT:
In a circuit configuration for clock-controlled time division multiplex telecommunications switching installations, including PCM telephone switching installations with central switching network and connected subswitching networks, line groups are connected to a central switching network via time division multiplex lines and have one subswitching network and one group control unit each are pairwise assigned to each other. Line units which are individually assigned to the one or the other of two line groups are, in normal operation, connected to the subswitching network of their own line group and can be changed over to the subswitching network of the particular other line group in standby operation. In the line units, equalizing memorys are provided in duplicate and, specifically, in each instance for the message stream to and from line group-common subswitching network, on the one hand, and for the message stream to and from the subswitching network of the particular partner line group. The equalizing memories receive the pulse clock for their clock-controlled output processes in each instance from that subswitching network to which they output their messages. First equalizing memories receive their pulse clock from their own line group; second equalizing memories receive their pulse clock from the particular partner line group.

REFERENCES:
patent: 4488292 (1984-12-01), Troost
patent: 4670871 (1987-06-01), Vaidya
patent: 4905220 (1990-02-01), Junge et al.
patent: 4905222 (1990-02-01), Seeger et al.
patent: 4914429 (1990-04-01), Upp
patent: 5010550 (1991-04-01), Hirata
"telcom report", supplement to the fourth volume (1981).

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