Circuit configuration employing a compare unit for testing varia

Details Circuit configuration employing a compare unit for testing varia Circuit configuration employing a compare unit for testing varia

1994-03-11

1996-10-29

Trammell, James P.

Boots, shoes, and leggings

371 1, 371 27, 371 24, 327270, 327276, 327277, 324527, H03H 1126

Patent

active

055702945

ABSTRACT:
A test configuration is provided which allows a plurality of variable delay units within a delay chain to be compared with respect to one another. The delay chain is employed within a clock generator circuit that generates internal clock signals of a microprocessor. During normal operation, a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. During a test operation when it is desired to test the variable delay units for possible defects, the four delay units are electrically separated from one another by setting the multiplexers in a test mode. A common test signal is then driven through two or more of the variable delay units simultaneously, and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time. If no manufacturing defects are present, the four outputs of the variable delay units should be virtually indistinguishable from one another. Similar tests may be conducted throughout the entire operating range of the variable delay units.

REFERENCES:
patent: 5349612 (1994-09-01), Guo et al.
patent: 5374860 (1994-12-01), Llewellyn
patent: 5389843 (1995-02-01), McKinney
patent: 5430394 (1995-07-01), McMinn et al.

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