Circuit configuration and method for reducing the 1/f noise...

Amplifiers – With semiconductor amplifying device – Including field effect transistor

Reexamination Certificate

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C330S010000

Reexamination Certificate

active

07012468

ABSTRACT:
The circuit configuration and the associated method allow reducing the 1/f noise of MOSFETs in an electronic circuit, especially in an integrated circuit with one or more MOSFETs. At least one direct current and/or at least one direct voltage source for adjusting constant working point(s) of the MOSFET(s) is/are assigned to one or more or all MOSFETs. At least one periodically oscillating current and/or voltage source is assigned to one or more or all MOSFETs so that the respective working points periodically oscillate about the constant working point(s) in such a manner that impurity states in the oxide of the MOSFET, which are recharged under the condition of a constant working point according to the principles of statistics such that they determine the 1/f noise signal, are no longer recharged statistically but at a lower probability due to the modulatory frequency of the periodically oscillating sources.

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Bram Nauta et al.: “Reduction of 1/f Noise in MOSFETs by Switched Bias Techniques”,Proceedings 17thNORCHIP Conference, Oslo, Norway, Nov. 8, 1999, pp. 60-72.
Sander L. J. Gierkink et al.: “Intrinsic 1/f Device Noise Reduction and Its Effect on Phase Noise in CMOS Ring Oscillators”,IEEE Journal of Solid-State Circuits, vol. 34, No. 7, Jul. 1999, pp. 1022-1025.
I. Bloom et al.: “1/f noise reduction of metal-oxide-semiconductor transistors by cycling from inversion to accumulation”,Appl. Phys. Lett., vol. 58, No. 15, Apr. 15, 1991, pp. 1664-1666.
Gierkink, S.L.J., et al.: Reducing MOSFET 1/f Noise and Power Consumption by “Switched Biasing”, 25thEuropean Solid-State-Circuits Conference, The Hague, Netherlands, pp. 154-157.

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