Circuit configuration and method for priority selection of inter

Details Circuit configuration and method for priority selection of inter Circuit configuration and method for priority selection of inter

1992-04-20

1993-06-08

Fleming, Michael R.

Boots, shoes, and leggings

395275, 395325, 3642412, 3642413, 364240, 3642401, 364DIG1, G06F 1326

Patent

active

052187039

ABSTRACT:
A circuit configuration and a method for priority selection of interrupts for a microprocessor in an integrated circuit which includes a central processing unit, a central interrupt node connected to the central processing unit, N interrupt sources for presenting interrupt requests to the central processing unit, peripheral interrupt nodes each being connected to a respective one of the N interrupt sources. A common interrupt bus is connected to the peripheral interrupt nodes and to the central interrupt node. The method for priority selection includes activating the interrupt bus in a prioritizing round in accordance with a priority value with a peripheral interrupt node assigned to an interrupt source in the presence of an interrupt request of the interrupt source.

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