Circuit configuration and a method for the testing of storage ce

Details Circuit configuration and a method for the testing of storage ce Circuit configuration and a method for the testing of storage ce

1988-03-16

1990-01-23

Lastova, John R.

Excavating

365200, 365201, G11K 2900

Patent

active

048963224

ABSTRACT:
In a circuit configuration and a method for testing storage cells, all of the bit lines lead to one pair of fault lines which is first precharged with mutually-complementary logic levels. All of the storage cells of a word line are always read-out in parallel relative to one another. In the event of "no fault" the pair of fault lines retains its logic states, whereas in the case of a fault one of the fault lines changes its logic state through switching transistors. This is recognized and analyzed by a comparator circuit in the form of an XOR-circuit or an XNOR-circuit.

REFERENCES:
patent: 4055754 (1977-10-01), Chesley
patent: 4685086 (1987-08-01), Tran
Y. You, "A Self-Testing Dynamic RAM Chip", IEEE Transactions on Electronic Devices, vol. 32, No. 2, 2/1985, pp. 508-515.
Patent Abstracts of Japan, vol. 6, No. 188 (P-144), [1066], Sep. 28, 1982; and Japanese 57-100690 (Tokyo Shibaura Denki K. K.), Jun. 22, 1982; Summary.

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