Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means
Reexamination Certificate
2002-05-08
2004-07-27
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular chip input/output means
C257S786000, C257S782000, C257S459000, C257S202000, C257S207000, C257S208000, C257S211000, C257S784000, C257S779000, C257S780000, C257S773000, C257S775000, C257S776000, C257S691000, C438S128000, C438S129000, C438S612000, C438S666000
Reexamination Certificate
active
06768142
ABSTRACT:
FIELD
This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to input output cell design and placement for integrated circuits.
BACKGROUND
The surface of an integrated circuit such as an ASIC or an ASSP can be logically divided into two different portions, being the input output of the integrated circuit, and the core
20
of the integrated circuit as depicted in
FIGS. 4 and 5
. As depicted in
FIG. 1
, the input output of the integrated circuit
10
a
includes input output cells
14
a
that are connected to bonding pads
16
, such as by lines
18
, and to the core
20
of the integrated circuit
10
a
, such as by lines
22
. Thus, all communication with the core
20
of the integrated circuit
10
a
is typically handled through the input output of the integrated circuit
10
a.
Integrated circuits are typically categorized as being either input output limited, as depicted in
FIG. 4
, or core limited as depicted in FIG.
5
. An input output limited integrated circuit
10
a
, as depicted in
FIG. 4
, is one in which the size of the substrate on which the integrated circuit is formed is predominantly determined by the space required by the input output cells
14
a
. In other words, any additional input output cells
14
a
required by an input output limited integrated circuit
10
a
results in an increase in the size of the substrate. Typically, more than a single row of bonding pads
16
a
and
16
b
is required around the peripheral edge of an input output limited integrated circuit
10
a
. In an input output limited integrated circuit
10
a
, there is typically ample surface area for the space requirements of the core cells
20
.
On the other hand, a core limited integrated circuit
10
b
, as depicted in
FIG. 5
, is one in which the size of the substrate on which the integrated circuit
10
b
is formed is predominantly determined by the space required by the core cells
20
. In other words, any additional core cells
20
required by a core limited integrated circuit
10
b
results in an increase in the size of the substrate. Typically, only a single row of bonding pads
16
is required around the peripheral edge of a core limited integrated circuit
10
b
. In a core limited integrated circuit
10
b
there is typically ample surface area for the space requirements of the input output cells
14
a.
In an input output limited integrated circuit
10
a
(FIG.
4
), the input output cells
14
a
are typically narrow and tall, meaning that the length of the input output cell
14
a
along an edge that is substantially parallel to the peripheral edge
12
of the integrated circuit
10
a
tends to be appreciably shorter than the length of an edge that is substantially perpendicular to the peripheral edge
12
of the integrated circuit
10
a
such as depicted in FIG.
1
. In this manner, many input output cells can be placed along the length of the peripheral edges
12
of the integrated circuit
10
a
. Although the tall input output cells
14
a
tend to extend relatively far into the core
20
of the integrated circuit
10
a
this is typically not a problem because, as mentioned above, there tends to be ample surface area for the core components of an input output limited integrated circuit
10
a.
On the other hand, the tall and narrow design of an input output cell that is optimized for an input output limited integrated circuit is extremely inefficient for a core limited integrated circuit. The reason for this is that in a core limited integrated circuit, the input output cells may be more widely spaced apart, because fewer of them are required. Thus, there tends to be a large amount of wasted surface area between the narrow input output cells in such a design. However, as mentioned above, the tall input output cells tend to extend relatively far into the core of the integrated circuit, which for a core limited integrated circuit is already densely populated. Thus, the height of the tall and narrow input output cells requires the overall size of the substrate on which the integrated circuit is formed to be larger to accommodate the length of the input output cells. Because there is wasted space between the input output cells, this tends to result in a very inefficient use of the substrate surface area, and unnecessarily increases the cost of production of the integrated circuit.
A better design for an input output cell
14
b
of a core limited integrated circuit
10
b
would be a relatively wide, relatively short input output cell
14
b
, as depicted in
FIG. 2
, which design is substantially the opposite of the aspect ratio of the input output cell
14
a
designed for an input output limited integrated circuit
10
a
. However, because most integrated circuits tend to be input output limited rather than core limited, there are typically many input output cell designs that are available for use in an input output limited integrated circuit
10
a
design.
Because it is complicated and time consuming to develop a new input output cell design, and such a design for a core limited integrated circuit would tend to be used very little, many designers just use the input output cells that are designed for input output limited integrated circuits, even when they have a core limited integrated circuit, so that they do not have to take the time and expense of designing an input output cell for the core limited integrated circuit. Although this results in an integrated circuit that is more expensive than is necessary, it is often less expensive than taking the time to create a new core limited input output cell design.
Adding to this problem is the surface area on the substrate which is taken by the corner cells
24
, where input output cells
14
cannot be placed, as depicted in FIG.
3
. The corner cells
24
are typically disposed in the corners of the integrated circuit
10
, where the buss lines, such as VSS
32
, VDD
30
, IDDtn (not depicted so as to enhance the clarity of the figure), VDDio
28
, and VSSio
26
are turned at the corner from tracking in a parallel fashion a first peripheral edge
12
a
of the integrated circuit
10
to an adjoining second peripheral edge
12
b
of the integrated circuit
10
that is perpendicular to the first peripheral edge
12
a
. Because the buss lines
26
,
28
,
30
, and
32
cut through the corner cell
24
at an angle, a standard input output cell
14
cannot be placed in the corner region inhabited by the corner cell
24
, because it would not make proper electrical connections with the buss lines
26
,
28
,
30
, and
32
, which are not disposed in the same positions in the corner regions as they are along the peripheral edges.
Thus, there is a need for integrated circuit designs and elements that overcome these and other problems.
SUMMARY
The above and other needs are met by a method for designing an input output cell of an integrated circuit. The input output cell has a required area, a width, and a height. The bonding pad pitch length between adjacent bonding pads of the integrated circuit is measured. The width of the input output cell is specified to be substantially equal to the bonding pad pitch length. The required area is divided by the width to determine a first value, and the height of the input output cell is specified to be substantially equal to the first value.
In this manner, the width of the input output cells is no greater than the distance between two adjacent bonding pads, and thus the input output cells can be placed very close together, facilitating their use in input output limited integrated circuit designs. However, the height of the input output cells is no greater than is necessary to enclose the required area of the input output cell, thus facilitating their use in core limited integrated circuit designs. In various preferred embodiments, the bonding pads for the input output cells are disposed within their surface areas, thereby further reducing the surface area of the integrated circuit that is required for the input output functions of the integrated ci
Ali Anwar
Huang Wei
Lau Tauman T.
Nguyen Ken
Yeung Max M.
Im Junghwa
Loke Steven
LSI Logic Corporation
Luedeka Neely & Graham
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