Circuit carrier and fabrication method thereof

Details Circuit carrier and fabrication method thereof Circuit carrier and fabrication method thereof

2006-09-05

2006-09-05

Lee, Eddie C. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S697000, C257S690000, C257S778000, C257S779000, C257S781000, C257S775000, C257S692000

Reexamination Certificate

active

07102230

ABSTRACT:
A circuit carrier adapted for a pin grid array (PGA) package is disclosed. The circuit carrier comprises a substrate, at least one pin pad, at least one solder mask layer, at least one solder layer, at least one pin and a fixing layer. The pin pad is disposed over the surface of the substrate. The solder mask layer is disposed over the surface of the substrate, and exposing at least a portion of the pin pad. The solder layer is disposed over the pin pad. One end of the pin connects to the pin pad through the solder layer. The fixing layer is disposed over the solder mask layer, and covering the solder layer and a portion of a side surface of the pin. When the solder layer melts due to a high process temperature, the fixing layer helps to fix the pin to the pin pad.

REFERENCES:
patent: 6543676 (2003-04-01), Tung et al.
patent: 6720500 (2004-04-01), Inoue
patent: 6911726 (2005-06-01), Rumer et al.

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