Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2007-11-27
2007-11-27
Smoot, Stephen W. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257SE23173, C361S763000, C361S782000
Reexamination Certificate
active
11020226
ABSTRACT:
A laminating step includes a second step of laminating a second insulation layer on a conductive pattern last formed at a first step, roughening the surface of the laminated second insulation layer excluding a desired area, and forming a conductive layer on at least the desired area of the surface of the second insulation layer, and a processing step includes a removing step of removing an upper part of the area higher than the second insulation layer on the substrate obtained at the laminating step, and an exposing step of exposing a part of the area of a conductive pattern adjacent to the lower side of the second insulation layer.
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N. Wakabayashi; “The trend and technical development of a high-density multilayer resin substrate package;” NE/NμD Hardware Conference 2002; May 30, 2002; draft paper (6 sheets) with extract./Discussed in the specification.
European Search Report dated Jun. 27, 2007.
Notice of Reasons for Rejection dated Jul. 3, 2007 corresponding to Japanese patent application No. 2004-263729.
Fujitsu Limited
Kratz Quintos & Hanson, LLP
Smoot Stephen W.
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