Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-06-07
2003-01-28
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S668000, C257S672000, C257S676000, C257S680000, C257S690000, C257S723000, C257S737000, C257S738000, C257S774000, C257S784000, C257S797000
Reexamination Certificate
active
06512288
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a circuit board for making semiconductor packages and, more particularly, to a circuit board that is designed to facilitate mass production of a large number of semiconductor packages on a single circuit board.
2. Description of the Related Art
In general, a circuit board for semiconductor packages has circuit patterns formed on the surface of a base material, such as a resin layer, film or tape. The circuit patterns are coated with a cover coat except where solder connections are subsequently made.
A semiconductor chip is mounted on the circuit board, followed by wire bonding and encapsulation with a sealant for protecting the semiconductor chip against the external environment. The resulting circuit board is provided with input/output means, such as conductive balls or conductive pins, and then mounted on a motherboard.
Examples of known semiconductor packages that are made using a circuit board include a ball grid array semiconductor package, a chip scale semiconductor package, and a micro ball grid array semiconductor package.
It is conventional that only about 5 to 10 semiconductor packages are fabricated on a single circuit board, which is subsequently singulated to make individual packages. This gives a low production yield. In addition, the completed semiconductor packages are thick because the semiconductor chips are mounted on the surface of the circuit board.
Recognition marks, which serve as base points in a process for connecting the semiconductor chips and the circuit patterns of the circuit board, are formed in the circuit patterns in the vicinity of a portion where the semiconductor chips are mounted. Unfortunately, the position is hard to recognize, which results in bondwire connection errors.
Furthermore, there are some cases where cracks or other damage occurs during the process of punching forming slots that serve as a boundary of the respective semiconductor packages.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a circuit board for making semiconductor packages that allows simultaneous fabrication of a large number of semiconductor packages, accurate singulation of the individual packages, and a reduction in the connection (wire bonding) error rate.
It is another object of the present invention to provide a circuit board for making semiconductor packages that facilitates the formation of sub slots which serve as a common boundary of the respective packages and which prevents cracks or damage to the circuit patterns during the process of forming the sub slots.
To achieve the above objects of the present invention and others, one embodiment of the present invention provides a circuit board for making semiconductor packages. The exemplary circuit board includes: a resin layer in the form of a rectangular sheet with first and second sides, the resin layer having plurality of package units each having a through hole and arranged in rows and columns sharing a sub slot of a predetermined length as a common boundary to form one sub strip for mounting a semiconductor chip, a plurality of the sub strips being arranged in a row and sharing a main slot of a predetermined length as a common boundary to form one main strip; a plurality of circuit patterns each formed in the resin layer between the through hole of the individual sub strip and the surrounding sub slots; and a cover coat coated on the resin layer for the purpose of protecting the circuit patterns against external environments.
A metal film can be formed on the first side of the resin layer between the through holes and the sub slots.
Here, each of the circuit patterns includes a plurality of bond fingers which will be connected to the semiconductor chip later, and a plurality of ball lands which will be fused to conductive balls later, wherein the bond fingers and the ball lands are exposed from the cover coat. Also, each of the circuit patterns includes the bond fingers and the ball lands formed on the second side of the resin layer; or alternatively includes the ball lands on the first side of the resin layer, and the bond fingers formed on the second side of the resin layer. The bond fingers are connected to the ball lands through conductive via holes in the latter embodiment.
The resin layer further includes a plurality of notches having a predetermined depth between the plural sub slots located in the periphery of the through hole.
A metal film can also be formed on the first side of the resin layer with the ball lands formed thereon.
The notches are vertical to the lengthwise direction of the individual sub slot.
The resin layer further includes a recognition mark serving as a base point during a wire bonding, between the plural sub slots located in the periphery of the through hole.
The recognition mark may be a circuit pattern in the form of “+”.
The circuit board further includes a plurality of ground rings formed on the first side of the resin layer around the periphery of the individual through holes, the ground rings being connected to at least one circuit pattern.
Also, the circuit board further includes a plurality of ground planes exposed from the cover coat in the periphery of the individual sub strips, the ground planes being connected to at least one circuit pattern.
A ground plane can also be formed on the first side of the resin layer with the ball lands formed thereon.
To achieve the above objects of the present invention, there is also provided a circuit board including: a resin layer in the form of a rectangular sheet with first and second sides; a plurality of circuit patterns arranged in rows and columns separated from each other at a predetermined distance in both first and second sides of the resin layer or in either one of the first and second sides, to form one sub strip, a plurality of sub strips being arranged in a row to form one main strip; a conductive bus pattern formed in the first side or the second side of the resin layer between the circuit patterns separated from each other at a predetermined distance in the sub strip, the bus pattern being connected to all end portions of the circuit patterns; and a cover coat of a predetermined thickness coated on a portion of the resin layer where the circuit patterns are formed, and exposing a defined portion of the bus pattern and the resin layer outer than the bus pattern.
Here, the defined portion of the bus pattern and the resin layer outer than the bus pattern exposed from the cover coat is a region that will be punched into the sub slot later.
The defined portion of the bus pattern and the resin layer outer than the bus pattern exposed from the cover coat is larger in area than the sub slot to be formed later.
The coat line of the cover coat accross the circuit lines of the circuit patterns adjacent to the bus pattern has an irregular shape, e.g., a square wave shape.
According to the present invention, a plurality of through holes on which a semiconductor is mounted constitute one sub strip and a plurality of the sub strips are connected in a row to constitute one main strip, as a consequence of which a large number of semiconductor packages are produced on a single circuit board.
A plurality of notches formed in the resin layer between the sub slots in the periphery of the through holes facilitate singulation of the circuit board during a singulation process of the semiconductor packages after an encapsulation process. Also, recognition marks formed in the resin layer between the sub slots allow connection equipment, for example, wire bonding equipment to accurately recognize the positions of the semiconductor chips and the circuit board, thereby providing an accurate wire bonding (electrical connection) between the semiconductor chips and the circuit board.
Furthermore, because there is not cover coat applied to a portion where the sub slots will be formed later, prior to forming the sub slots in the circuit board, the sub slot forming (punching) process can be easily performe
Chun DoSung
DiCaprio Vincent
Jang TaeHoan
Lee Seon-Goo
Shin WonSun
Amkor Technology Inc.
Sefer Ahmed N.
Skjerven Morrill LLP
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