Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-08-07
2002-02-26
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C361S749000, C361S750000, C361S751000, C324S754090, C324S757020
Reexamination Certificate
active
06350957
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit board having patterns in the form of bumps with a very narrow variation-in height projecting from at least one surface thereof, and more specifically, to a circuit board formed having high-reliability conduction structures between its general output and input terminals and conductor circuits and which is capable of high-density packaging of semiconductor devices. The present invention also relates to a bump-type contact head obtained with use of the circuit board, capable of satisfactorily checking even fine-pitch circuit components, such as LSIs, liquid crystal panels, TABs, PDPs, etc., for wiring failures, and which enjoys high accuracy in pitches between inspection terminals and excellent high-frequency characteristics. In addition , the present invention relates to a method for manufacturing these elements with high productivity and at low cost.
Still further, the invention relates to a semiconductor component packaging module of a novel connection structure, using the aforesaid circuit board as a packaging substrate and having various semiconductor components mounted on the substrate by die bonding.
2. Prior Art
Usually, a semiconductor device package, which may be incorporated in various electronic apparatuses such as a computer, portable communication apparatus, liquid crystal panel, etc., is constructed so that one semiconductor device, such as a bare chip, is mounted on a circuit board that is formed with predetermined patterns for conductor circuits, the continuity between this device and the respective output and input terminals of the conductor circuits is established to package the semiconductor device, and the whole structure is resin-molded.
The semiconductor device may be packaged by a method in which it is die-bonded to the circuit board and the output and input terminals of the circuit board and the terminals (lands) of the semiconductor device are wire-bonded, a method in which a flip chip is connected to the output and input terminals of the circuit board by, for example, soldering, or a method in which the output and input terminals of the circuit board and lead terminals of the semiconductor device are directly connected by soldering.
The semiconductor device package manufactured in this manner is incorporated in practical equipment by being mounted on a mother board (packaging substrate) on which the conductor circuits with the predetermined patterns are arranged. Usually, in this case, the area ratio of one semiconductor device package to the mother board ranges from about {fraction (1/10)} to ⅕, so that a plurality of semiconductor device packages can be mounted on the mother board.
Conventionally, wire bonding is partially used for the mounting on the mother board. To meet the requirement for high-density packaging, however, a novel method has recently started to be widely used such that cream solder is pattern-printed on the lands of the mother board, the terminals (lead terminals or ball grid arrays) of the semiconductor device package are registered on the resulting pattern, and the whole resulting structure is subjected to blanket soldering in a reflow device.
There is a growing tendency for modern electronic apparatuses to become smaller in size, higher in operating speed, and more diverse in function. Accordingly, there is an increasing demand for the development of circuit boards capable of high-density packaging of semiconductor components despite the smallness in overall size.
To this end, it is advisable to use multilayer circuit boards and fine-pattern conductor circuits to be formed. Usually, however, conventional multilayer circuit boards are manufactured by the so-called build-up method, so that they involve the following problems.
In manufacturing a multilayer circuit board by the build-up method, a unit circuit board is first prepared by forming a conductor circuit, which serves as a signal pattern, on the surface of an insulating substrate as a bottom layer. Another unit circuit board, which is formed with another conductor circuit as another signal pattern, is put on the first one for unification. This operation is repeated so that a plurality of unit circuit boards are successively assembled from bottom to top.
In this case, a conduction structure between conductor circuits in each two adjacent layers, upper and lower, usually includes a plurality of through holes bored in a predetermined plane pattern through the unit circuit board in the thickness direction thereof. After the wall surface of each through hole is given electrical conductivity by, for example, electroless plating, electroplating is carried out with use of the conductor circuit in the lower layer as an electrical conduction path, and the respective lands of the conductor circuits in the upper and lower layers are connected electrically by means of the resulting deposit.
In order to effect the high-density packaging, therefore, the through holes should be made small in diameter. Practically, however, the hole diameter can be reduced only limitedly.
Generally, the through holes are formed by drilling, so that their diameter cannot be made very small in consideration of the drilling strength. Normally, the diameter of drilled holes ranges from 150 to 200 &mgr;m. The diameter of through holes formed by photolithography ranges from about 100 to 150 &mgr;m.
In the case where a deposit is formed on the wall surface of each bored through hole by combining the electroless plating and electroplating, it must secure a certain measure of thickness, since the electrical continuity between the conductor circuits in the upper and lower layers cannot be satisfactory if the deposit is too thin. For good electrical conduction between the conductor circuits, the thickness of the deposit is normally adjusted to about 20 to 30 &mgr;m, depending on the type of the circuit board.
In general, therefore, a deposit with a thickness of 15 to 20 &mgr;m is formed on the surface of each through hole with a diameter of 150 to 200 &mgr;m, in the conduction structure based on the through holes. In the center of each through hole, in this case, exists a dead space with a diameter of about 100 to 150 &mgr;m that has no connection with the conduction between the conductor circuits at all.
Also in the case of inner via holes, a dead space with a diameter of about 60 to 70 &mgr;m is created if the diameter of each hole is, for example, 100 &mgr;m. Thus, the diameter of the conventional through holes or inner via holes can be reduced only limitedly, and has no effect on the conduction between the conductor circuits, inevitably.
Normally, the following operation is carried out to form the deposit on the wall surface of each through hole in each of inner layers that are built up in succession. After electrical conductivity is given to the whole surface of a target inner layer (including the wall surface of each existing through hole or inner via hole) by electroless plating, a thin deposit is formed by electroplating the inner layer surface. Then, a dry film, for example, is sticked on the surface of the deposit so as to cover it, and is exposed and developed to expose only those portions corresponding to the through holes. The resulting structure is further electroplated with the remaining portion masked, whereupon a deposit of a given thickness is formed on the surface of each through hole (and land). Thereafter, the dry film is separated, and the thin deposit on the exposed surface of the inner layer and the deposit formed by the electroless plating are removed by, for example, soft etching.
In manufacturing a multilayer circuit board by building up the individual inner layers, therefore, the aforesaid operation must be repeated for each inner layer, so that complicated manufacturing processes are required. Thus, the manufacture takes long time, inevitably entailing high manufacturing costs.
In the case of the inner via holes, solid conduction structures may be formed between the layers by forming a d
Aoshima Katsuro
Shingai Noboru
Wada Tatsuo
Frishauf, Holtz Goodman, Langer & Chick, P.C.
Gaffin Jeffrey
Meiko Electronics Co., Ltd.
Vigushin John B.
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