Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1997-03-28
2003-12-09
Talbott, David L. (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S250000, C174S255000
Reexamination Certificate
active
06660944
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit board having solder balls or bumps such as for flip-chip bonding and ball grid array. Further, the present invention relates to a method of producing such a circuit board. Still further, the present invention relates to a flattening and leveling jig used for carrying out the method.
2. Description of the Related Art
In case of mounting, for example, an integrated circuit chip on an integrated circuit board, it is known to form on their joining surfaces a plurality of terminals of a grid pattern or checkered pattern and bond them by way of the terminals, i.e., a technology that is called flip chip.
Further, it is also known, in case of joining an integrated circuit board having installed thereon an integrated circuit chip to a printed circuit board such as a motherboard, a bonding technology of forming on a back surface of the integrated circuit board (i.e., a joining surface opposite to the front surface on which the integrated circuit chip is installed) a plurality of terminals which are bonding balls of high melting point solder, Cu or the like and arranged so as to form a grid pattern, for thereby bonding the integrated circuit board to the printed circuit board, such a board being called a ball grid array (BGA) board.
Various technologies such as a solder paste technology are known for forming such an integrated circuit board or the like having terminals adapted for surface-to-surface joining and arranged so as to form a grid or checkered pattern.
For example, as shown in
FIG. 15A
, the solder paste technology includes a process of applying solder paste onto conductive base pads formed on an integrated circuit board by printing and thereafter melting the paste by heating for thereby forming semi-spherical or spherical solder bumps on the pads.
However, forming the solder bumps in the above described manner includes problems described hereinafter and improvement thereof has been eagerly required.
(1) Generally, it has been considered desirable that solder bumps formed on an integrated circuit board are equal in height to each other for the purpose of improving the joining or bonding ability or the like to be joined or bonded to the integrated circuit chip or the printed circuit board. That is, as shown in
FIG. 15B
, it has been considered desirable that the coplanarity “d” of all of the solder bumps “p” is small.
In this connection, the term “coplanarity” is expressed or represented by the distance “d” between two parallel surfaces S
1
and S
2
between which the tops or apices of all the solder bumps “p” are included, and is used as an index for indicating the irregularity in the height or level of the solder bumps. In this invention, a coplanarity per unit length, which is obtained by dividing the coplanarity by the maximum distance between the solder bumps (i.e., normally, the diagonal distance of the area in which the solder bumps are formed) since the coplanarity depends on the area in which the solder bumps are formed.
However, the height of each solder bump of itself varies depending upon the volume of solder applied to each pad and the size of the pad, etc., so that a variation in the volume of solder, the size of the pad, etc. causes the solder bumps to become irregular in height. Accordingly, there is caused a problem in that the coplanarity becomes larger. A further problem is that even if the solder bumps are equal in height a large coplanarity results in case the board is warped or curved.
When the coplanarity is large, a joining defect may possibly be caused since the distance between the terminals standing opposite to each other becomes irregular at the time of joining the integrated circuit board to the integrated circuit chip or the printed circuit board. Further, even in case a probe is made to contact respective solder bumps with a view to examining the conduction of the conductors and the insulation between the conductors, it becomes difficult for the probe to contact predetermined solder bumps or all the solder bumps at the same time, so there occurred a case in which accurate measurement could not be obtained.
(2) An image processor is used for measurement of the coplanarity of the solder bumps for the purpose of examining the joining ability of the integrated circuit board but includes a problem in that since the top of the solder bump is constituted by a curved surface it is difficult to detect the highest point or apex of the solder bump and it is inevitable to set at least three points to which a laser beam is irradiated even in the case the highest point (apex) is obtained by approximation, causing a problem in that much labor is required.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a circuit board which comprises a substrate having a joining surface, and a plurality of solder bumps disposed on the joining surface of the substrate in such a manner as to form a predetermined profiled line or surface pattern, wherein the solder bumps have tops which are flattened and leveled, and a coplanarity of the solder bumps is 0.5 &mgr;m or less per 1 mm. In this connection, the term “solder” is herein used to mean or indicate Pb—Sn based soft solder and other low melting point solders in a broad sense, such as Au—Sn solder, Au—Si solder, etc. Further, the term “circuit board” is intended to indicate not only (1) a board on which an integrated circuit chip is mounted but (2) a board to be joined with a printed circuit board and (3) an integrated circuit chip of itself (i.e., flip chip). More specifically, indicated by that term are (1) a board having, at one side surface thereof, a plurality of solder bumps for joining to an integrated circuit chip or chips (flip chip bonding), (2) a board having, at one side surface thereof, a plurality of solder bumps (usually, BGA), for joining to a printed circuit board, and (3) an integrated circuit chip having a plurality of solder bumps. The above described profiled line pattern is for example a square frame-like pattern. The profiled surface pattern is for example a grid pattern or checkered pattern.
According to a further aspect of the present invention, circular pads are interposed between the solder bumps and the substrate to serve as base layers of the solder bumps.
According to a further aspect of the present invention, the tops of the solder bumps have nearly circular flat surfaces which are smaller in diameter than the pads.
According to a further aspect of the present invention, the tops of the solder bumps have nearly circular flat surfaces which are substantially equal in diameter to the pads, and the height of the solder bumps is smaller than the diameter of the pads.
According to a further aspect of the present invention, there is provided a method of producing a circuit board including a substrate having a joining surface, and a plurality of solder bumps disposed on the joining surface of the substrate in such a manner as to form a predetermined pattern, wherein the solder bumps have tops which are flat and leveled, and a coplanarity of the solder bumps is 0.5 &mgr;m or less per 1 mm. The method comprises the steps of placing masses of solder on the solder bumps, respectively, disposing a control member in the form of a flat plate at a predetermined position above the masses of solder, and forming the masses of solder into the solder bumps all at once by melting the masses of solder and allowing the control member to control the height of the solder bumps while flattening the tops of the solder bumps all at once. The above described solder material can be solder paste, solder preform, solder ball, one having been already formed into solder bump, or the like. The material for the above described control member can be a metal such as titanium and stainless steel, ceramics such as alumina, silicon nitride and silicon carbide, glass and the like, and such one that is not wetted by solder or has a difficulty in being wetted by solder is suitable therefor. Particular
Inaishi Masashi
Kimura Yukihiro
Murata Haruhiko
NGK Spark Plug Co. Ltd.
Norris Jeremy
Talbott David L.
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