Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2001-09-17
2002-08-27
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S698000, C257S737000, C257S747000, C257S780000, C257S781000
Reexamination Certificate
active
06441493
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor packaging technology and, more particularly, to a BGA (Ball Grid Array) package.
2. Description of Related Art
As higher performance, more reliable, smaller and lighter IC devices are increasingly required, demands for smaller component packages and higher input/output (I/O) pin counts are increasing in the semiconductor packaging industry. The QFP (Quad Flat Package) and the BGA (Ball Grid Array) package offer a large number of I/O pins, as required by modem IC technology. In order to accommodate the increasing number of I/O pins, the QFP technology is forced to an ever finer lead pitch, which results in increasingly thinner, more fragile leads. Accordingly, the BGA package is more proper for a high I/O pin-count requirement while keeping the overall size of the package device smaller, using a far coarser pitch and more-freely-designed interconnections. The BGA package is an area array package that utilizes whole or part of the device footprint for interconnections made of balls composed of a conductive material such as a solder alloy. The BGA package is advantageous in that it can obtain the chip scale or chip size package (CSP) by reducing the package size by more than 30 percent of the normal lead frame plastic package and make the ball pitch less than 1.00 mm.
In a BGA package, reliability is important, in particulars the reliability of the solder joint, e.g., the joint between the solder ball and the ball land, is critical. When the solder joint is disconnected, electrical path is disconnected, resulting in undesirable device failure. Further, if cracks occur in the solder joint, electrical resistance in the joint increases and thus electrical characteristics of the device cannot be assured. The increase of the resistance in the joint produces an unwanted DC voltage drop in the signal path and may cause a charging delay in RC circuits and noise in system level.
Several attempts have been made to strengthen the joint between the solder balls and ball lands. One such example is disclosed in U.S. Pat. No. 5,796,163, in which a metal-to-metal annular bond is formed at the joint between the solder ball and the land around the plug of nonconductive material in the center of a via. Such a technology is also disclosed in U.S. Pat. No. 5,875,102, U.S. Pat. No. 5,936,848 and U.S. Pat. No. 5,706,178.
In U.S. Pat. No. 5,875,102, each via hole has a portion located within a solder pad to increase the routing space of the substrate, and additionally a portion located outside the solder pad to allow outgassing from the via hole. U.S. Pat. No. 5,936,848 discloses a technology using a plug via hole, while U.S. Pat. No. 5,706,178 describes a via hole structure formed within the solder ball land. Additionally, in U.S. Pat. No. 5,872,399, a dimple is formed in the solder ball land, and in U.S. Pat. No. 6,028,366, a groove is formed in the ball land. The purpose of both methods is to increase the joint strength between the solder ball and the ball land.
However, these conventional methods have not been fully successful in achieving a level of package reliability that is required by recent integrated circuit technology.
SUMMARY OF THE INVENTION
It is, therefore, an object of this invention to improve the package reliability, e.g. the reliability of the joints between solder balls and ball lands.
It is another object of this invention to prevent cracking from occurring in the joints between the solder balls and the ball lands.
For the purposes of the present invention, the inventors focus on the fact that the reliability of the BGA package largely depends on the package pad design. After reviewing and analyzing the causes of the cracks in the joints, the inventors discovered that the joint cracks occur in a direction to which a stress is applied. The inventors recognized that when a stress is applied to the joint in an arrow direction as shown in
FIG. 2
, the circle denoted as ‘A’ in the joint, i.e., the initial stressed portion of the joint is most susceptible to cracking. The stress may be applied, for example, because of a mismatch between the coefficient of thermal expansion (CTE) between the substrate
12
and the semiconductor chip
20
during thermal cycling in the reliability test of the package. In the reliability test, the package is subjected to heat and then cooled in room temperature.
According to the present invention, a circuit board has a chip mounting surface in which wiring patterns are formed and a solder ball mounting surface in which a plurality of solder balls are mounted and electrically interconnected to the wiring patterns. The circuit board comprises a plurality of ball lands each directly connected to the respective one of the solder balls; a older ball opening area defined by a solder ball mask generally deposited on the solder ball mounting surface and exposing the ball land from the solder ball mask; a plurality of pattern connecting portions each connected to corresponding one of the ball lands; and conductive wiring patterns linked together with the pattern connecting portions and electrically interconnected to the solder balls. The plurality of pattern connecting portions are arranged toward a center point of the solder ball mounting surface.
In an aspect of the present invention, a ball grid array package comprises the circuit board having centrally directional solder ball land types. The BGA package is a NSMD (non-solder mask defined) structure in that the size of the ball land is smaller than the ball land opening area.
REFERENCES:
patent: 5706178 (1998-01-01), Barrow
patent: 5796163 (1998-08-01), Glenn et al.
patent: 5875102 (1999-02-01), Barrow
patent: 5936848 (1999-08-01), Mehr et al.
patent: 6028366 (2000-02-01), Abe
patent: 6268568 (2001-07-01), Kimn
Ho Hoai
Ho Tu-Tu
Marger Jonhson & McCollom, P.C.
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