Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-04-24
2002-11-19
Cuneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S262000
Reexamination Certificate
active
06483046
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to circuit board technology, and more particularly, to a circuit board wherein a leading edge of the plated through hole is off-set from a surface of the circuit board, to prevent burr formation.
2. Related Art
Castellated plated through holes located at the periphery of a substrate or circuit board are commonly used in circuit technology for various applications. For instance, castellated plated through holes may be used when coupling adjacent circuit boards, thereby providing a solder inspection joint to ensure the solder “wicks up” properly at the interface of the two boards.
Various methods are currently used to create castellated plated through holes at the edges of circuit boards. For instance, a castellated plated through hole may be formed by injection molding, or by cutting, milling, drilling, blanking, etc., the edges of the circuit board. However, as illustrated in
FIG. 1
, conventional methods tend to produce a circuit board
1
, wherein protruding burrs
3
are formed in the castellated plated through holes
2
.
FIG. 2
illustrates a prior art profiling tool
4
, rotating in the direction indicated by arrows
5
, approaching a plated through hole
7
within circuit board
1
from a lateral direction indicated by arrow
6
. As shown in
FIG. 3
, burr formation results when profiling tool
4
, moving along a path
11
, begins to break through a leading edge
8
of inner hole wall
9
. “Leading edge” refers to the first surface or edge of plated through hole
7
contacted by profiling tool
4
. Once leading edge
8
of plated through hole
7
has been severed, the only forces available to resist profiling tool
4
are the adhesive forces located between inner hole wall
9
and a layer of copper laminate
10
plated thereon. The heat generated as profiling tool
4
completes the pass through plated through hole
7
, causes copper laminate
10
to detach and pull away from inner hole wall
9
at leading edge
8
. This occurs because the adhesive forces between copper laminate
10
and inner hole wall
9
at leading edge
8
are not sufficient to hold copper laminate
10
in place.
FIG. 4
shows the loose flap of copper laminate at leading edge
8
of plated through hole
7
folded over and protruding into the center of castellated plated through hole
2
, resulting in what is commonly referred to as a “burr”
3
.
The problems associated with burr formation include the potential to dislodge and short circuit the device, interference with inspection of solder joints, contamination of further processing steps, and so on.
Based on the above, there is a need for a new method of creating castellated plated through holes in circuit boards which does not result in burr formation.
SUMMARY OF THE INVENTION
The present invention provides a circuit board that overcomes the above-identified problems of the related art by, in general, pre-profiling the plated through hole, thereby removing the leading edge of the plated through hole to prevent burr free formation during the subsequent profiling operation.
The first general aspect of the present invention provides a method of producing a circuit board having burr free castellated plated through holes, comprising the steps of: providing the circuit board having at least one plated through hole therein; removing a lengthwise portion of the at least one plated through hole; and profiling the at least one plated through hole, leaving a recessed portion at an edge of the circuit board. This aspect allows for the creation of a circuit board having castellated plated through holes at the periphery, without the burr formation associated with conventional methods.
The second general aspect of the present invention provides for a method of producing a burr free castellated plated through hole, comprising the steps of: providing a circuit board having at least one plated through hole therein; removing a lengthwise section of a vertical wall of the at least one plated through hole; and removing a portion of the at least one plated through hole, leaving a recessed portion within an edge of the circuit board. This aspect allows for similar advantages as those associated with the first aspect.
The third general aspect of the present invention provides for a circuit board having at least one burr free castellated plated through hole formed by removing a first portion of an at least one plated through hole, and removing a second portion of the at least one plated through hole, leaving a recessed portion within an edge of the circuit board. This aspect provides a circuit board which allows for similar advantages as those associated with the first aspect.
It is therefore an advantage of the present invention to provide a method of forming burr free castellated plated through holes in the periphery of a circuit board.
It is therefore a further advantage of the present invention to provide conventional circuit boards having castellated plated through holes which have unobstructed inspection joints and provide a reduced risk of shorts.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention.
REFERENCES:
patent: 3185947 (1965-05-01), Freymodsson
patent: 3311791 (1967-03-01), Larson et al.
patent: 3357099 (1967-12-01), Nagy et al.
patent: 3357856 (1967-12-01), Ragan et al.
patent: 4288841 (1981-09-01), Gogal
patent: 4372046 (1983-02-01), Suzuki
patent: 4525597 (1985-06-01), Abe
patent: 4543715 (1985-10-01), Iadarola et al.
patent: 4572757 (1986-02-01), Spadafora
patent: 4790894 (1988-12-01), Homma et al.
patent: 4821007 (1989-04-01), Fields et al.
patent: 4852227 (1989-08-01), Burks
patent: 4913931 (1990-04-01), Frederickson
patent: 5069626 (1991-12-01), Patterson et al.
patent: 5140745 (1992-08-01), McKenzie, Jr.
patent: 5434745 (1995-07-01), Shokrgozar et al.
patent: 5499446 (1996-03-01), Murakami
patent: 5499447 (1996-03-01), Murakami
patent: 5570505 (1996-11-01), Downie et al.
patent: 6263565 (2001-07-01), Gotoh et al.
patent: 5-267847 (1983-10-01), None
patent: 4-148591 (1992-05-01), None
patent: 4-56380 (1992-09-01), None
Houser David E.
Larnerd James M.
Lee Jeffrey L.
Poch Francis S.
Cuneo Kamand
Fraley Lawrence R.
Schmeiser Olsen & Watts
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