Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
2000-08-23
2002-10-22
Caneo, Kamand (Department: 2827)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S260000
Reexamination Certificate
active
06469258
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit board for a semiconductor a package and, more particularly, to a circuit board for semiconductor package having a structure that completely grounds corresponding equipment used in the manufacture of semiconductor packages based on the circuit board, thereby preventing a breakdown of the semiconductor chip or circuit board due to electrostatic discharge (“ESD”).
2. Description of the Related Art
Generally, a circuit board for semiconductor package fixedly supports a semiconductor chip mounted on a main board, and intermediates required electrical signals between the semiconductor chip and the main board. During manufacturing of the package, a plurality of circuit board units are joined in one strip, and the packages are made in parallel. The individual circuit board units usually include an insulative thermosetting resin substrate or film coated with a copper circuit pattern on both sides thereof. Portions of the circuit pattern are coated with a cover coat on both sides.
Recently developed semiconductor chips operate with a low driving voltage and small acceptable voltage error. Unfortunately, such semiconductor chips or circuit boards upon which the chips are mounted are susceptible to a breakdown due to electrostatic charges accumulated and discharged during the process for assembling the semiconductor package, e.g., during wire bonding, molding, marking, ball bumping and singulation.
For example, during the encapsulation step, there may be direct friction between a polymer-based encapsulating material and a cover coat or conductive layer of the circuit board (e.g., signaling, grounding and powering circuit patterns) or the semiconductor chip, resulting in electrostatic charges being accumulated on the circuit board or semiconductor chip. The circuit board with accumulated electrostatic charges is then taken off from a mold for the subsequent step, during which procedure the conductive parts of the circuit board get in contact with the mold or another conductive material, which causes an abrupt discharge of the electrostatic charges, thereby damaging the semiconductor chip or circuit board. Such a large discharge of electrostatic charges may occur in all steps of the process, but more frequently occurs during the encapsulation step of the circuit board when using a mold.
To solve this problem, referring to
FIGS. 9A and 9B
, a method has been suggested to provide separately coated index holes
16
(
FIG. 9A
) or a ground plate
17
(
FIG. 9B
) in circuit board unit
2
or strip
100
. Expediently, it is illustrated in the figures that the coated index hole and the ground plate are provided on a single circuit board strip.
In
FIG. 9A
, on a resinous substrate is formed an approximately square chip mounting region
8
to mount a semiconductor chip on, with close and fine conductive circuit patterns
10
radially arranged in the periphery of the chip mounting region
8
. Between the circuit patterns
10
is provided a gold gate
40
connected to the chip mounting region
8
or the circuit pattern
10
, especially, grounding pattern and providing a passage for the encapsulating material flowing from the edge of the respective circuit board units
2
towards the chip mounting region
8
. The chip mounting region
8
and the circuit patterns
10
on the resinous substrate are coated with a cover coat
6
, while the end portions of the circuit patterns
10
electrically connected to the gold gate
40
and the semiconductor chip are open to the exterior without cover coat
6
. A defined portion of the circuit patterns
10
has a conductive via hole
12
downwardly formed in the resinous substrate (in the drawing, the via holes
12
are formed just inside dash line
36
), and a plurality of ball lands
14
(to be fused to conductive balls) are connected to the via hole
12
on the underneath of the resinous substrate. The overall bottom surface of the resinous substrate other than ball lands
14
is also coated with the cover coat
6
.
In
FIGS. 9A and 9B
, reference numeral
22
denotes a slot having a desired length formed between the respective circuit board units
2
, reference numeral
18
denotes a singulation hole used as a baseline of the circuit board strip
100
cut into semiconductor packages, reference numeral
16
denotes an index hole used to fix or load the circuit board on various equipment, and dash line
36
denotes the perimeter of an encapsulation region.
The index hole
16
, which has its inner wall coated with metal, is connected to a grounding circuit pattern
10
. Also, the individual index hole
16
receives a fixed pin provided on equipment every time the circuit board is set in the equipment, so that the metallic equipment gets in electrical contact with the index hole
16
of the circuit board, causing the electrostatic charges to move from the circuit board or semiconductor chip to the equipment.
However, as the index hole
16
is slightly larger in diameter than the fixed pin of the equipment, and taking the fixed pin out of the index hole
16
in an intended manner or not makes the grounding status unstable temporarily, with the potential of discharging a large amount of charges.
On the other hand, as shown in
FIG. 9B
, a ground plate
17
having a desired area is formed in the individual units
2
containing a plurality of ball lands
14
as well as the coated index hole
16
. When loading the circuit board on the corresponding equipment, the ground plate
17
gets in ground contact with a conveying rail or a loading portion of the equipment. The ground plate
17
is of course connected to the grounding circuit pattern. However, there are some worse cases where warpage of the circuit board strip renders the grounding status unstable between the ground plate
17
and the equipment, resulting in a breakdown of the circuit board of semiconductor package.
SUMMARY OF THE INVENTION
An object of the present invention to solve the problems with the prior art is to provide a circuit board for semiconductor package capable of easily moving electrostatic charges generated during an encapsulation step from the circuit board or semiconductor chip to a mold.
Another object of the present invention is to provide a circuit board for semiconductor package designed to provide a complete grounding with corresponding equipment in the manufacture of the semiconductor package based on a circuit board, thereby preventing a breakdown of the circuit board or semiconductor chip caused by electrostatic charges.
To achieve the above objects and others, there is provided a printed circuit board for semiconductor package including: a resinous substrate; a chip mounting region formed on the top surface of the resinous substrate for mounting a semiconductor chip thereon; a plurality of fine circuit patterns radially disposed in the circumference of the chip mounting region and extending to the edge of the chip mounting region; a plurality of ball lands formed in an array on the bottom surface of the resinous substrate, to be fused to conductive balls; a conductive via hole connecting the circuit patterns on the top surface of the resinous substrate to the ball lands on the bottom surface of the resinous substrate; a cover coat applied to the top and bottom surfaces of the resinous substrate to protect the circuit patterns from an external environment and make the ball lands open to the exterior; and a means for removing electrostatic charges provided at the edge of the substrate and connected to the plural circuit patterns to remove electrostatic charges in the manufacture of semiconductors.
In another aspect of the present invention, the circuit board may have a matrix form, in which a plurality of the circuit boards are connected in series with a slot interposed therebetween to constitute a strip, and a plurality of the chip mounting regions are separated at a defined distance from one another and collectively arranged in rows and columns to constitute one sub strip, wherein a plural
Jang Tae Hoan
Ko Chang Hoon
Lee Choon Heung
Lee Seon Goo
Lee Won Kyun
Amkor Technology Inc.
Caneo Kamand
Norris Jeremy
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