Circuit board features with reduced parasitic capacitance and me

Details Circuit board features with reduced parasitic capacitance and me Circuit board features with reduced parasitic capacitance and me

1998-12-31

2000-08-15

Gulakowski, Randy

Etching a substrate: processes

Forming or treating electrical conductor article

Forming or treating of groove or through hole

216 19, 430313, 430314, 430318, H05K 306

Patent

active

061031348

ABSTRACT:
A method for fabricating circuit board conductors with desirable processing and reduced self and mutual capacitance. The method generally entails forming a metal layer on a positive-acting photodielectric layer formed on a substrate, and then etching the metal layer to form at least two conductor traces that cover two separate regions of the photodielectric layer while exposing a third region of the photodielectric layer between the two regions. The third region of the photodielectric layer is then irradiated and developed using the two traces as a photomask, so that the third region of the photodielectric layer is removed. The two remaining regions of the photodielectric layer masked by the traces remain on the substrate and are separated by an opening formed by the removal of the third dielectric region. As a result, the traces are not only separated by a void immediately therebetween formed when the metal layer was etched, but are also separated by the opening formed in the photodielectric layer by the removal of the third region of the photodielectric layer. Traces formed in accordance with the above may be formed as adjacent and parallel conductors or adjacent inductor windings of an integral inductor.

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