Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1999-04-02
2001-11-06
Gaffin, Jeffrey (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S770000, C361S777000, C361S782000, C257S686000, C257S723000, C257S724000
Reexamination Certificate
active
06313998
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the production of circuit board assemblies and electronic modules, such as memory modules, and more particularly to a method and apparatus for attaching integrated circuit packages to printed circuit boards. It also relates to high-density memory modules having three-dimensional arrangements of integrated circuit packages.
BACKGROUND OF THE INVENTION
Demand for semiconductor memory is highly elastic. When such memory is relatively inexpensive compared to the overall cost of a computer system, an almost unsatiable demand results, with computer manufacturers tending to install an amount of main memory in each system that greatly exceeds the amount required for average program use. On the other hand, when it is costly, manufacturers typically install an amount in each system that only marginally fulfills the requirement of the average program. Although the sales prices of computers may, thus, be maintained at low levels, the end user may soon find that he must upgrade his computer's main memory.
The ever increasing demand for large random access computer memories, and the growing demand for increasingly compact computers, coupled with an incentive on the part of the semiconductor manufactureres to reduce the cost per bit, has lead to not only a quadrupling of circuit density approximately every three years, but to increasingly efficient techniques for packaging and mounting the circuit chips. Up until the late 1980's, semiconductor memory chips were usually packaged as dual in-line pin packages (DIPPs). The pins of these DIPP packages were generally soldered directly within through-holes in a main circuit board (e.g., the motherboard), or they were inserted in sockets which were, in turn, soldered within through-holes in the main circuit board. With the advent of surface mount technology, conventional plated through-holes on printed circuit boards have been replace with conductive mounting pads. Small Outline J-lead (SOJ) packages have lead to Thin Small Outline Packages (TSOPs). Because the pitch or spacing between centers of adjacent surface mount pins is significantly less than the conventional 0.10-inch spacing for conventional through-hole components, surface mount chips tend to be considerably smaller than corresponding conventional chips, thus taking up less space on a printed circuit board. Additionally, as through holes are no longer needed, surface mount technology lends itself to the mounting of components on both sides of a printed circuit board. Memory modules utilizing surface-mount packages on both sides have become the standard. Both the earlier single in-line memory modules (SIMMs) and the currently used dual in-line memory modules (DIMMs) are inserted into sockets on the motherboard.
Packaging density may be increased rather dramatically fabricating modules in which a plurality of integrated circuit (IC) chips, such as memory chips, are stacked in a three dimensional arrangement. As a general rule, the three-dimensional stacking of chips requires complex, non-standard packaging methods.
One example of a vertical stack of IC chips is provided by U.S. Pat. No. 4,956,694 to Floyd Eide, titled INTEGRATED CIRCUIT CHIP STACKING. A plurality of integrated circuits are packaged within chip carriers and stacked, one on top of the other, on a printed circuit board. Except for the chip select terminal, all other like terminals on the chips are connected in parallel.
Another example of chip stacking is given in U.S. Pat. No. 5,128,831 to Fox, et al. titled HIGH-DENSITY ELECTRONIC PACKAGE COMPRISING STACKED SUB-MODULES WHICH ARE ELECTRICALLY INTERCONNECTED BY SOLDER-FILLED VIAS. The package is assembled from individually testable sub-modules, each of which has a single chip bonded thereto. The sub-modules are interleaved with frame-like spacers. Both the sub-modules and the spacers have alignable vias which provide interconnection between the various sub-modules.
U.S. Pat. No. 5,313,096, also issued to Floyd Eide and titled IC CHIP PACKAGE HAVING CHIP ATTACHED TO AND WIRE BONDED WITHIN AN OVERLYING SUBSTRATE, is another example. Such a package includes a chip having an upper active surface bonded to the lower surface of a lower substrate layer having conductive traces on its upper surface which terminate in conductive pads on its periphery. Connection between terminals on the active surface and the traces is made with wire bonds through apertures within the lower substrate layer. An upper substrate layer, which is bonded to the lower substrate layer, has apertures which coincide with those of the lower substrate layer and provide space in which the wire bonding may occur. After wire bonding has occurred, the apertures are filled with epoxy to form an individually testable sub-module. Multiple sub-modules can be stacked and interconnected with metal strips attached to their edges.
A final example of a stacked-chip module is disclosed in U.S. Pat. No. 5,869,353 to A. U. Levy, et al. titled MODULAR PANEL STACKING PROCESS. A plurality of panels are fabricated having apertures therein, an array of chip-mounting pads at the bottom of the apertures, and interfacing conductive pads. Both the chip-mounting pads and the interfacing conductive pads are coated with solder paste. Plastic-encapsulated surface-mount IC chips are positioned on the paste-covered mounting pads, multiple panels are stacked in a layered arrangement and the stack is heated to solder the chip leads to the mounting pads and the interfacing pads of adjacent panels together. Individual chip package stacks are then separated from the panel stack by a cutting and cleaving operation.
As can be seen by the foregoing examples, increased chip density is achieved through the use of complicated packaging and stacking arrangements, which must necessarily be reflected in a higher costs per bit of storage.
SUMMARY OF THE INVENTION
The present invention provides for an improved circuit board assembly having increased chip density. A preferred embodiment of the improved assembly is fabricated with standard plastic-encapsulated, surface-mount IC chips using conventional circuit board assembly techniques. The assembly includes a printed circuit board having at least one primary mounting pad array affixed thereto, each pad of said primary array having first and second portions; a first integrated circuit (IC) package having a package body and a plurality of primary leads attached to the package body, each of which is conductively bonded to the first portion of a different mounting pad of said primary array; a package carrier positioned above the first IC package, the carrier having a carrier body with a package mounting surface thereon, a plurality of carrier leads attached to the carrier body, and a secondary mounting pad array affixed to the package mounting surface, each carrier lead being coupled to a different pad of said secondary mounting pad array, each carrier lead being conductively bonded to the second portion of a different mounting pad of said primary array; and a second integrated circuit package having a plurality of secondary leads, each of which is conductively bonded to a different mounting pad of said secondary array. The first and second IC packages are of identical shape and configuration.
The invention may be utilized to increase memory density on memory modules. For other types of IC packages, it may be employed to more efficiently utilize available real estate on a printed circuit board. In the case of packages containing memory chips, each lead, with the exception of chip select leads, is directly coupled to a corresponding lead on the other package. In order maintain chip select signals separate for each package, the first and second portions of the chip select pad on the first array are not coextensive, but rather are insulated from one another.
Variations of both basic embodiments are possible. For example, the leads of surface mount IC packages may vary. Two types of leads are most commonly used for surface mount components. One lead is “J”-sha
Engle Jason C.
Kledzik Kenneth J.
Gaffin Jeffrey
Legacy Electronics, Inc.
Vigushin John B.
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