Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
1998-07-16
2002-04-16
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S846000, C427S097100, C205S126000, C205S157000, C205S187000
Reexamination Certificate
active
06370768
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a novel circuit board, whereon semiconductors and the like are mounted, and a method of manufacturing the same; and more particularly, the invention relates to a circuit board having via-holes filled with metal for connecting interlayer conductor wiring, and a method of manufacturing the same.
The technology to fill holes, which are formed in an insulator, with metal is applied to the technology for interlayer connection of high density circuit boards, such as a LSI, a thin film multilayered board, a build up board, and the like. For the interlayer connection of an LSI, wet metallizing methods, such as plating and the like, are not used, but dry metallizing such as spattering, CVD (chemical vapor deposition method), and the like are used. For instance, a method of filling aluminum into via-holes by the spattering method is disclosed in JP-A-6-168907 (1994). A method of filling tungsten into contact holes by a monosilan reduction CVD method of tungsten fluoride, or hydrogen reduction CVD method is disclosed in JP-A-8-31932 (1996). Furthermore, a method of forming a connecting plug of copper by a CVD method using an organo copper compound as a raw material is disclosed in JP-A-6-236879 (1994).
However, since all these methods are dry metallization methods and methods for processing which use an apparatus provided with a vacuum system, these methods have problems, such as a high equipment cost and a low through-put. Furthermore, so-called PVD methods (physical vapor deposition method), such as a spattering method and the like, do not have selectivity in forming a film, and so a metallic film must be formed on the whole surface of the substrate uniformly. Therefore, it is impossible to metallize only the interlayer connecting portion. On the other hand, a film formed by the CVD method has problems, such as a large content of impurities and a low purity. The decrease in purity causes such problems as an increase in the electrical resistance and a decrease in the reliability.
Regarding thin film multilayered substrates and build-up substrates, a method of filling micro via-holes using the techniques of electroless plating or electroplating has been disclosed, but control of film thickness is difficult. For instance, In accordance with JP-A-6-302965 (1994), the via-holes are filled by plating. However, in this case, since the control of the plated film thickness is extremely difficult, a final polishing step is required. A method of filling the inside of via-holes by electroplating or electroless plating has been disclosed in JP-A-5-335713 (1993). However, in accordance with the above prior arts the filling of the via-holes by electroless plating is impossible. Because the electroless plating reaction proceeds also on the end plane of the conductor surface at the upper layer of the via-holes, the opening of the via-hole is decreased with elapsed plating time and finally is closed. In this case, a space in the form of a void remains inside the via-hole, and the reliability of the substrate is significantly decreased.
In the case of electroplating, the plating reaction proceeds at the end plane of the conductor surface at the upper layer of the via-holes from the moment when the metal plated from the bottom portion of the via-hole reaches the end plane of the conductor surface at the upper layer of the via-holes, and so the opening of the via-hole will become closed in those cases where the diameter of the via-hole is less than two times the conductor thickness. In this case, a space in the form of a void again remains inside the via-hole, resulting in a problem in that the reliability of the substrate is significantly decreased. When the diameter of the via-hole is larger than two times the conductor thickness, the opening of the via-hole will not become closed, but the shape of the plating, when it reaches the conductor surface, is not “columnar” like the shape when plating the inside of the via-hole, but is “a mushroom shape”. This is because the plating reaction does not indicate any anisotropy, but the metal grows in an isotropic manner.
As explained above, when filling metal into a micro hole using a dry metallizing method, problems occur in that the manufacturing steps become complex because the PVD method does not have selectivity, and so a polishing step becomes necessary, and in that the production yield is decreased because the stress applied to the substrate when polishing is significant. Because the CVD method uses a compound containing a chemical element other than a metal as the raw material, the obtained metal contains a large amount of impurities. The increase in impurity concentration causes problems, such as an increase in the electric resistance, a decrease in the reliability, and the like. The problems inherent in use of the metallizing method as a whole are a high apparatus cost, because the apparatus requires a vacuum system, and a low through-put.
On the contrary, when filling metal into a micro hole using a wet metallizing method, either the electroplating method or the electroless plating method can be used.
In accordance with the electroplating method, an electricity supplying layer for supplying an electric current for the plating is required as a base layer. A first conductive layer is previously not used for patterning, but necessarily is used as the electricity supplying layer first. Accordingly, the inside of the via-holes is filled by plating first, then, the insulating layer is peeled off, and patterning of the first conductive layer is performed. Subsequently, the insulating layer is formed again, and polishing is performed in order to flatten the surface and determine the via-hole filling metal. The polishing step is one of the problems, because the step requires a long time, and this decreases the production yield because the stress applied to the substrate is significant.
When the electroless plating method is used, the plating reaction proceeds from only the surface of a first conductive layer, and the inside of the via-hole is filled with the plated metal. In this case, a second conductive layer on the surface of the insulating layer is necessarily formed after filling the via-holes. Because, if the plating is performed in the presence of the second conductive layer, the plating reaction also will proceed from the surface of the second conductive layer, and the openings of the via-holes will close. When the plating reaction proceeds from the surface of the first conductive layer to fill the inside of the via-holes with the plated metal, control of the plated film thickness is extremely difficult. When the plated film thickness is small, a break in the wiring is possible, and when the plated film thickness is large, the flatness of the surface is lost, and so problems are generated informing the multilayered structure.
Therefore, in accordance with the prior art, the inside of the via-holes has been filled with metal by the steps of thickening the plated film thickness somewhat, causing the plated metal to protrude from the insulating layer, in order to eliminate possibility of a break in the wiring caused by deficiency of the plated film thickness, and subsequently, polishing off the excess portion of the plated metal to flatten the surface. However, the polishing step in this process requires a long time, as explained above, and the production yield is decreased by the significantly large stress applied to the substrate.
SUMMARY OF THE INVENTION
One of the objects of the present invention is to provide a circuit board, which makes it possible to identify via-hole portions, on the surface of a substrate, in order to facilitate formation of a multilayered structure with the substrate, which via-holes have been previously filled with metal.
The second object of the present invention is to provide a method of manufacturing a circuit board, which makes it possible to fill metal into the via-holes with good reproducibility and uniformly, by electroless plating, a process with which it has b
Antonelli Terry Stout & Kraus LLP
Arbes Carl J.
Hitachi , Ltd.
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