Circuit arrangement with MOS-transistors for the rapid evaluatio

Details Circuit arrangement with MOS-transistors for the rapid evaluatio Circuit arrangement with MOS-transistors for the rapid evaluatio

1980-07-23

1983-06-14

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307448, 365204, H03K 512, H03K 19094

Patent

active

043885411

ABSTRACT:
Circuit having MOS-transistors for the rapid evaluation of the logic state of a sampling node, including a circuit input connected to the sampling node, a circuit output, a supply voltage source, an inverter being connected to the circuit input and having an output, a first transistor being connected between the circuit input and the circuit output and having a gate connected to the output of the inverter, a second transistor being connected between the supply voltage source and the circuit output and having a gate connected to the output of the inverter, and a third transistor shunted across the second transistor as a load resistor.

REFERENCES:
patent: 3932848 (1976-01-01), Porat
patent: 4145622 (1979-03-01), Hofmann et al.

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