Circuit arrangement with at least one input and at least one out

Details Circuit arrangement with at least one input and at least one out Circuit arrangement with at least one input and at least one out

1994-04-15

1995-12-12

Chin, Stephen

Pulse or digital communications

Transceivers

370 8513, H04J 324, H04J 302

Patent

active

054757088

ABSTRACT:
A circuit arrangement (1000, 2000), preferably for a coupling network component of a network node in a packet-switching data network, is disclosed which has a wide parallelization of the data packet signal by means of shift registers (60), so that it is possible to operate internally with a greatly reduced operating speed. In particular, an arrangement of the components on a single semiconductor wafer (3000, 4000) permits an especially wide bus (20), which can be constructed extremely advantageously with a surface-optimized floor plan (3000, 4000).

REFERENCES:
patent: 4627052 (1986-12-01), Hoare et al.
patent: 4890280 (1989-12-01), Hirata
patent: 4962499 (1990-10-01), Sennema

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