Circuit arrangement with a test circuit and a reference...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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C324S076410, C324S076770

Reexamination Certificate

active

08081003

ABSTRACT:
Implementations are presented herein that include a test circuit and a reference circuit.

REFERENCES:
patent: 4139147 (1979-02-01), Franke
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patent: 5412663 (1995-05-01), Kromer et al.
patent: 5905855 (1999-05-01), Klaiber et al.
patent: 2009/0201094 (2009-08-01), Ohtsuka
S. Drapatz, G. Georgakos, D. Schmitt-Landsiedel; Impact of Negative and Positive Bias Temperature Stress on 6T-SRAM Cells; Adv. Radio Sci.; version 2.3 of the Latex class copernicus.cls.; Dec. 4, 2008; pp. 1-6.
T. Kim, R. Persaud, C. Kim; Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits; IEEE Journal of Solid-State Circuits, vol. 43, No. 4, Apr. 2008; pp. 874-888.
M. Ketchen, M. Bhushan; Product-representative “at speed” test structures for CMOS characterization; IBM J. Res. & Dev. vol. 50, No. 4/5 Jul./Sep. 2006; pp. 451-468.
A. Drake, R. Senger, H. Deogun, G. Carpenter, S. Ghiasi, T. Nguyen, N. James, M. Floyd, V. Pokala; A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor; ISSCC 2007; Session 22; Digital Circuit Innovations; 22.1; 2007 IEEE International Solid-State Circuits Conference; pp. 398-399.
K. Kang, K. Kim, A. Islam, M. Alam, K. Roy; Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement; DAC 2007, Jun. 4-8, 2007, San Diego, California, USA.

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