Circuit arrangement suitable for testing cells arranged in rows

Details Circuit arrangement suitable for testing cells arranged in rows Circuit arrangement suitable for testing cells arranged in rows

1991-07-29

1994-08-23

Teska, Kevin J.

Excavating

371 223, G01R 3128

Patent

active

053413830

ABSTRACT:
A circuit arrangement formed on an IC chip includes a first type block and a second type block. The first type block has a plurality of cells arranged into rows and columns and a plurality of transistors respectively provided for the cells. Each of the transistors has a first terminal coupled to a corresponding one of the cells, a second terminal and a gate terminal. The second type block is a block which is not required to be test in a way identical to that for the first type block. A probe line driver tests the cells in the first type block, and is located along a first edge of the first type block. A plurality of probe lines extend from the probe line driver and run in the first type block. Each of the probe lines is connected to the gate of a corresponding one of the transistors. A sense circuit senses data read out from the cells via a plurality of sense lines running in the first type block. Each of the sense lines is connected to the second terminal of a corresponding one of the transistors. The sense circuit is located along a second edge of the first type block substantially perpendicular to the first edge of the first type block. A test control circuit controls the probe line driver and the sense circuit so that data are successively read out from the cells and transferred to the sense lines via the transistors. The test control circuit is adjacent to the probe line driver and the sense circuit.

REFERENCES:
patent: 4710930 (1987-12-01), Hatayama et al.
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4739250 (1988-04-01), Tanizawa
patent: 4914379 (1990-04-01), Maeno
patent: 4972372 (1990-11-01), Ueno
patent: 5043986 (1991-08-01), Agrawal
patent: 5121394 (1992-06-01), Russell
patent: 5172377 (1992-12-01), Robinson et al.
patent: 5173904 (1992-12-01), Daniels et al.
patent: 5184067 (1993-02-01), Nozuyama
Proc. of the IEEE 1990 Custom Integrated Circuits Conference, May '90, Boston US, pp. 411-414; K. Pierce et al.: "High Performance CMOS Array With an Embedded Test Structure".
Proc. of the IEEE 1989 Custom Integrated Circuits Conference, May '89, San Diego, US, pp. 331-334; C. Ng et al.: "A Herarchical Floor-Planning, Placement, and Routing Tool for Sea-of-Gates Designs".

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