Pulse or digital communications – Pulse transmission via radiated baseband
Reexamination Certificate
2000-06-14
2004-05-25
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Pulse transmission via radiated baseband
C375S295000
Reexamination Certificate
active
06741657
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit arrangement for transmitting pulses via a transmission path.
2. Description of the Prior Art
In the digital technology, it is frequently a problem to transmit short pulses within integrated circuits or via interconnects of motherboards over longer paths. The longer the line—namely the transmission path—the more its lowpass effect takes effect, so that short pulses can only be tapped at the end of the transmission path in a strongly damped manner. This property becomes more disturbing as the pulses become shorter.
In order to be able to transmit the pulse cleanly, it is possible to dimension the driver correspondingly high. The capacity of the transmission path can be reloaded sufficiently fast by means of a correspondingly high driver. An insufficiently high driver reduces the amplitude of the transmitted pulse and therefore the signal-to-noise ratio, allowing jitter to easily occur. However, a high current demand is, disadvantageously, the result of a correspondingly high driver.
It is also possible to lengthen the pulse to be transmitted using a multi-stage delay circuit (as shown in FIG.
1
). For this purpose, the short pulses S
1
to be transmitted are directly supplied to the first input of an OR gate OR
1
and also are supplied to the second input of the OR element OR
1
via a delay element V. Pulses S
3
, which are lengthened by the delay time &Dgr;t, are then received at the output of the OR gate OR
1
. The lengthened pulses are then supplied to a second delay stage, whose structure corresponds to the first delay stage, so that pulse S
4
that is lengthened by the delay time 2*&Dgr;t is available to the transmission path US at the output of the second OR element OR
2
.
FIG. 2
shows the appertaining signal curves. If the input pulses S
1
are extremely short, the signal processing must ensue in a number of steps, since the OR gate generates undesired double-pulses given time delays &Dgr; that are larger than the pulse width. Disadvantageously, the dissipated power and the required chip surface increases with each additional delay stage.
German OS 40 20 719 discloses a method for transmitting a digital data signal with a frequency divider and a frequency multiplier having a delay element.
Japanese Application 63227113 discloses a circuit arrangement for transmitting pulses with a frequency divider, which has two flip-flops, and a frequency multiplier, which has an EXOR gate.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a circuit arrangement for transmitting pulses via a long transmission path wherein the above discussed disadvantages are avoided.
This object is inventively achieved in a circuit arrangement for transmitting pulses via a transmission path having a frequency divider having an input to which the pulses to be transmitted are supplied and having an output connected to the transmission path. In addition, a frequency multiplier is provided, whose input is connected to the transmission path and an output at which the transmitted pulses are present.
The frequency divider can be a first toggle-flip-flop.
In the inventive circuit arrangement, an output signal that is identical with respect to the signal to be transmitted regarding period length and pulse width can be generated in a simple manner at the output of the circuit arrangement. For this purpose, the frequency divider additionally includes a second toggle-flip-flop, with the pulses to be transmitted being supplied at the clock input of the first toggle-flip-flop and the output of the first toggle-flip-flop is connected to the transmission path. The pulses to be transmitted are supplied inverted at the clock input of the second toggle-flip-flop. For this purpose, an amplifier with complementary outputs precedes the toggle-flip-flops. The output of the second toggle-flop-flop is also connected to the transmission path. The frequency multiplier has an EXOR gate, with a first input and a second input connected to the transmission path. The transmitted signal can be tapped at the output of the EXOR gate.
Using an amplifier that has the complementary outputs and that precedes the toggle-flip-flops has the advantage that the toggle-flip-flops can be of the same edge control type. Therefore, the two toggle-flip-flops can be triggered on the low/high-edge (positively edge-triggered) or on the high/low-edge (negatively edge-triggered) in the respectively same way. As a result, the switching times of both toggle-flip-flops are identical and the pulse widths at the input and output therefore match given short pulses.
Each toggle-flip-flop can be realized as a simple edge-triggered D-flip-flop.
The inventive circuit arrangement can be formed as an integrated circuit.
REFERENCES:
patent: 4516236 (1985-05-01), Hadziomerovi
patent: OS 40 20 719 (1992-01-01), None
Patents Abstracts of Japan, E-705, Jan. 19, 1989, vol. 13/No. 23, for Japanese Application No. 62-61716.
Ghebretinsae Temesghen
Infineon - Technologies AG
Schiff & Hardin LLP
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