Circuit arrangement for time-division multiplex telecommunicatio

Multiplex communications – Wide area network – Packet switching

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370 66, H04Q 1104

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active

044674716

ABSTRACT:
Due to a control engineering context, write and read pulse frames of time-slot multiplexers of different switching matrix stages in a multi-stage, time-division multiplex switching matrix network exhibit coinciding pulse frame boundaries. In deviation therefrom, pulse frame boundaries of the pulse frames on switching network internal time-division multiplex lines are offset due to delays that are caused by serial-to-parallel and parallel-to-serial conversions of a partial information upon their intermediate storage in the time-slot multiplexer. Of two complete memories per time-slot multiplexer, one part of the one memory and another part of the other memory are inscribed during the pulse frame of an incoming time-division multiplex line. Auxiliary information is derived from an address (corresponding to the outgoing time channel) serving for the selection of a holding memory and form an address (corresponding to the incoming time channel) assigned for reasons of switching engineering and serving for the selection of a complete memory, the auxiliary information indicating from which of the complete memories the information to be forwarded is to be read so that, given multi-channel connection, the required sequence of the partial information is assured.

REFERENCES:
patent: 3573381 (1971-04-01), Marcus
patent: 4320501 (1982-03-01), LeDieu et al.
Geissler, H., "Contribution to Planning Pulse Code Modulation Systems . . . ", NTZ, No. 11, pp. 667-682.
Hessenmuller, H., Digital Sound Transmission", The Telecommunications Engineer, vol. 32, No. 11, pp. 1-36.
Kersten, R., "Pulse Code Modulation", Siemens Review XXXVIII, (1971), Special Issue Communications Engineering, pp. 186-194.

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