Circuit arrangement for the transmission of data signals

Details Circuit arrangement for the transmission of data signals Circuit arrangement for the transmission of data signals

1987-08-31

1989-11-14

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

370102, H04L 708, H04J 307

Patent

active

048812420

ABSTRACT:
A circuit arrangement includes a memory arrangement in which data signal bits forming the data signals can be read in at read-in times determined by a first clock pulse train and from which these data signal bits can be read out at read-out times determined by a second clock pulse train. A monitoring arrangement periodically and repetitively provides a test bit which can be read into or as the case may be out of the memory arrangements in parallel to the data signal bits. At its initialization, this monitoring arrangement enables the reading out of data signal bits previously entered in the memory arrangement with a delay, such that thereafter a predetermined phase relationship exists between test bits read into and read out of the memory arrangement. The monitoring arrangement provides a control signal which disables the memory arrangement lilmited in time with regard to the reading out of data signal bits and test bits when a defined predetermined change in this phase relationship is exceeded. Through such disabling, the defined phase relationship between test bits read in and read out is at least substantially reestablished.

REFERENCES:
patent: 4596026 (1986-06-01), Cease et al.
patent: 4718074 (1988-01-01), Mannas et al.
patent: 4791652 (1988-12-01), McEachern et al.
patent: 4811340 (1989-03-01), McEachern et al.

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