Circuit arrangement for the storage of digital data

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S051000, C365S189011

Reexamination Certificate

active

06795341

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
The present application claims priority from German patent application Serial Number DE 101 28 903.0 filed Jun. 14, 2001 and entitled “Circuit Arrangement for the Storage of Digital Data” which application is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
The Field of the Invention
The present invention relates to a circuit arrangement with an error correction device for the storage of digital data, in which the data to be stored are stored in storage locations or storage cells from which the stored data can be read by means of a read amplifier by collecting an electrical characteristic.
BRIEF SUMMARY OF THE INVENTION
With such a storage circuit several states can be stored in each storage location, for example a 1 information and a 0 information. Depending on the state that is stored in each case a storage location, in which the stored information is read with the aid of a current sensor amplifier, supplies two different, defined currents when reading. These defined currents are however achieved only after a specific time, after which a displacement current required to read the storage locations has decayed. If a storage location is read, then on account of the displacement current required for the reading the location current rises to a specific value and then falls depending on the state stored in the location to one of the two defined currents, the location current corresponding to a 0 information being lower than the location current corresponding to a 1 information. Similarly, the read amplifier may also collect a characteristic other than the current, such as for example a voltage and/or an electrical resistance.
The collected electrical characteristic during the reading process is accordingly value-continuous as well as time-continuous. In order to be able to obtain the stored digital datum from the location current the said location current is compared by means of a current sensor amplifier to a reference current, the output of the current sensor amplifier adopting a high value if the location current is less than the reference current, and adopting a low value as soon as the location current is less than the reference current. In order to evaluate the location current the displacement current must however first of all be allowed to decay.
The series-connected error correction device, being a processing device, receives at its input side the stored data from several storage locations and generates therefrom an error-corrected output signal. For the error correction the data may be redundantly stored in a manner that enables the correct data to be reconstructed also in the case of erroneous individual bits.
With storage locations that are read with a current sensor amplifier the curves describing the location currents can change in particular on account of leakage currents. Due to leakage currents electrical charges may flow in storage locations, with the result that the employed voltages of the transistors used for reading the storage locations and thus also the location current occurring during the reading may change. In particular it may happen that the location currents corresponding to the various items of information are increased. As a result the location current after the decay of the displacement current falls to in each case higher values and moreover falls more slowly. In the case of a stored 0 information the time may therefore be extended arbitrarily, following which the location current falls below the reference current. If leakage currents arise in the circuit arrangement, after the beginning of the reading of the storage locations the current sensor amplifier may switch over at an unspecified time. Since the individual current sensor amplifiers do not necessarily switch over at the same time and also switch over at unspecified times, defective corrections may arise with a series-connected error correction device if for example the switching-over of the current sensor amplifiers has not been completed early enough. In this case insufficient time remains between the last switching-over of a current sensor amplifier and a time at which the output signal of the error correction device is collected and/or intermediately stored, in order to carry out the error correction in the error correction device.
The object of the present invention is accordingly to provide a circuit arrangement for the storage of digital data of the type mentioned in the introduction in which the error security can be increased, especially also in the event of storage location leakage currents.
This object is achieved according to the invention by a circuit arrangement having the features of claim
1
.
Due to the interconnection of a register between the read amplifier and/or a current sensor amplifier and the processing device, in particular an error correction device, a signal that is both value-discrete as well as time-discrete is present at the input of the processing device. In this way during the processing of the data and/or during the error correction procedure the input signal of the error correction device can therefore be prevented from altering and leading to errors in the error correction. If a perturbed storage current occurs in one or more storage locations, in which the location current does not reach the correct value within the course of the reading procedure, then although a false state of the storage locations is intermediately stored by the register, nevertheless this can be corrected by the error correction device provided that not too many storage locations have been incorrectly read.
The registers may in this connection be controlled so that they intermediately store the output signal of the current sensor amplifier a specific time after the beginning of the reading procedure. This time period is adjusted so that the displacement currents have decayed. If however as a result of leakage currents the location currents are raised, the location current corresponding to the 0 information do not fall below the reference current.
In order to effect a correct adjustment of the register a control device may be associated with the circuit arrangement that controls the register a specific time after the start of the reading process in such a way that it can intermediately store the output signal of the current sensor amplifier.
The present invention may be used particularly advantageously with EEPROM memories, in which the danger of increased location currents is relatively great. The invention may be used especially with EEPROM memories that employ Fowler-Nordheim tunnels for programming and cancelling. In order in such cases to work with a low voltage a thin layer of tunnel oxide is as a rule used, whereby in turn the probability of a statistically accidentally occurring leakage current path in a storage location greatly increases. This is also termed “moving bit”.


REFERENCES:
patent: 5509134 (1996-04-01), Fandrich et al.
patent: 5604702 (1997-02-01), Tailliet
patent: 5784705 (1998-07-01), Leung
patent: 5986918 (1999-11-01), Lee
patent: 5996108 (1999-11-01), Tanzawa et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6317364 (2001-11-01), Guterman et al.
patent: 6349059 (2002-02-01), Bartoli et al.
patent: 2002/0013876 (2002-01-01), Rosa

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