Circuit arrangement for the routine testing of an interface betw

Details Circuit arrangement for the routine testing of an interface betw Circuit arrangement for the routine testing of an interface betw

1991-02-08

1992-09-08

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

370 15, 370 16, 371 205, H04J 314

Patent

active

051464748

ABSTRACT:
The interfaces between line terminator groups of a pair of redundant line terminator groups each comprise an interface circuit which makes it possible, by being equipped with a write-read memory, a switch-over device and a control device that controls these components, to test the interface parts belonging to an active line terminator group in a spot-check fashion during a time channel reserved for this purpose and to test the interface parts belonging to the passive line terminator group during all time channels on the basis of a respective check word mirroring.

REFERENCES:
patent: 4071704 (1978-01-01), Moed
patent: 4688208 (1987-08-01), Kawaguchi
patent: 4688209 (1987-08-01), Banzi, Jr. et al.
patent: 4860333 (1989-08-01), Bitzinger et al.
patent: 4953195 (1990-08-01), Ikemori

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