Circuit arrangement for the recognition of static and dynamic fa

Details Circuit arrangement for the recognition of static and dynamic fa Circuit arrangement for the recognition of static and dynamic fa

1984-08-24

1986-10-28

Fleming, Michael R.

Excavating

371 20, G06F 1100

Patent

active

046203036

ABSTRACT:
A central control unit that is connected with a number of circuit assemblies and has two interrupt inputs. Of these interrupt inputs, at first, when the circuit assemblies are in a fault-free state, only the one with the lower interrupt priority is activated. A register is provided, into which, when the circuit assemblies are driven by the central control unit, data with regard to the precise circuit assembly that is being driven in each case can be written. In addition, there is provided at least one fault recognition circuit, which when a fault exists in the respective circuit assembly, emits a fault signal when that assembly is driven. Connected with the abovementioned interrupt inputs is a control device, which, in response to such a fault signal, effects, through the activated interrupt input, the performance of a first interrupt routine, in the course of which the interrupt input with the higher interrupt priority is activated. Before the completion of the interrupt routine then in progress, the circuit assembly designated by the data in the register is driven again. If, a fault signal again occurs when this is done, the control device effects the performance of another interrupt routine through the interrupt input that has just been activated.

REFERENCES:
patent: 4308581 (1981-12-01), Raghunathogn
patent: 4377845 (1983-03-01), Markham
patent: 4410938 (1983-10-01), Higashiyama
patent: 4535456 (1985-08-01), Bauser
Hinz, et al., "Program Interrupted by Instruction Address Monitoring", IBM Tech Disclosure Bulletin, vol. 13, No. 4, Sep. 1970.

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