Circuit arrangement for the reception of data

Details Circuit arrangement for the reception of data Circuit arrangement for the reception of data

1975-11-18

1977-12-06

Atkinson, Charles E.

Communications: electrical

Digital comparator systems

G06F 1100

Patent

active

040619974

ABSTRACT:
A circuit arrangement for data transmission systems is described wherein the transmission of excessively faulty data signals is recognized and prevented, thereby stopping the transmission of senseless text. A fault discriminator emits a fault signal which is subsequently integrated. The integrated fault signal, if it exceeds a predetermined value, triggers a threshold value stage to produce a blocking signal. The blocking signal acts on the circuitry in a data sink, e.g., a teleprinter, to suppress the processing of the received data.

REFERENCES:
patent: 3036290 (1962-05-01), Zarouni
patent: 3159811 (1964-12-01), James et al.
patent: 3439327 (1969-04-01), Sourgens
patent: 3534403 (1970-10-01), Matarese
patent: 3573727 (1971-04-01), Freeny
patent: 3618015 (1971-11-01), Homonick
patent: 3829777 (1974-08-01), Muratani et al.
patent: 3863215 (1975-01-01), McGrogan, Jr.
patent: 3934224 (1976-01-01), Dulaney

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