Circuit arrangement for the protection of inputs of integrated M

Details Circuit arrangement for the protection of inputs of integrated M Circuit arrangement for the protection of inputs of integrated M

1976-08-25

1977-12-06

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307304, 330207P, 361 56, H02H 904, H03K 3353

Patent

active

040619281

ABSTRACT:
A circuit arrangement for the protection of inputs of integrated MOS circuits against excessive voltages, for example as a consequence of static charges, includes a first circuit means connected to the MOS circuit and having two bypass circuits reacting at different input voltage values and having a high-ohmic compensating resistance, and second circuit means is connected ahead of the first circuit and comprises a bypass circuit and a high-ohmic compensating resistance.

REFERENCES:
patent: 3395290 (1968-07-01), Farina et al.
patent: 3676742 (1972-07-01), Russell et al.
patent: 3712995 (1973-01-01), Steudel
patent: 3947727 (1976-03-01), Stewart
patent: 3967295 (1976-06-01), Stewart
Lenzlinger, "Gate Protection of MIS Devices"; IEEE Trans. on Electron Devices; vol. ED-18, No. 4, pp. 249-257; 4/1971.
Fischer, "Resistor-Thick Oxide FET Gate Protection Device for Thin Oxide FET"; IBM Tech. Discl. Bull.; vol. 13, No. 5, pp. 1272-1273.

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