Circuit arrangement for the formation of check bits for binary d

Details Circuit arrangement for the formation of check bits for binary d Circuit arrangement for the formation of check bits for binary d

1978-12-19

1981-06-02

Malzahn, David H.

Excavating

G06F 1110

Patent

active

042715172

ABSTRACT:
The invention relates to a circuit arrangement for coding or decoding comprising apparatus for forming check bits with the use of a linear code. The coding should be capable of adaptation to a desired coding scheme in the simplest manner. The invention provides a binary memory which stores each digit position of the binary information and has an allocated check digit position word. There is connected to the output side of the memory a modulo-2-adder cricuit for the purpose of adding check digit position words, and depending upon the binary information received, indicates whether or not it is correct. A circuit arrangement in accordance with the invention is particularly suited for utilization in remote control installations.

REFERENCES:
patent: 3798597 (1974-03-01), Frumbs et al.
patent: 3825893 (1974-07-01), Bossen et al.
patent: 3893070 (1975-07-01), Bossen et al.
patent: 4160236 (1979-07-01), Oka et al.
Jones, "Redundancy Checking by Table Look-Up", IBM Technical Disclosure Bulletin, vol. 13, No. 11, Apr. 1977, pp. 3322-3323.
Siemens, Datenbuch 1974/75, vol. 1, pp. 191-193 & 226-229.
Siemens, Datenbuch 1977/77, System SAB 8080, pp. 63-64, 219-220 & 256-259.

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