Circuit arrangement for the discrete-time comparison of signals

Details Circuit arrangement for the discrete-time comparison of signals Circuit arrangement for the discrete-time comparison of signals

2005-11-22

2005-11-22

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

Reexamination Certificate

active

06967506

ABSTRACT:
The invention pertains to a circuit arrangement (comparator) for the discrete-time comparison of input signals (ip, vrefp) and for making available a pair of complementary output levels (vdd, vss) which corresponds to the result of the comparison on a line pair (P, N), wherein said circuit arrangement comprises a reset circuit (12) for balancing the line potentials during a reset phase, an input circuit (14) for generating a potential difference on the line pair (P, N) in accordance with an input signal difference, a first bistable flip-flop (16) for amplifying the generated potential difference and a second bistable flip-flop (20) that is connected by means of a connecting circuit (18) and serves for additionally amplifying the generated potential difference to the desired complementary output levels.According to the invention, a third bistable flip-flop (30a, 30b) is provided that, when connecting the second flip-flop (20) parallel to the first flip-flop (16), amplifies the generated potential difference and thusly reduces the comparison time without significantly impairing the current consumption.

REFERENCES:
patent: 6396310 (2002-05-01), Shin
patent: 6507224 (2003-01-01), Lee et al.
patent: 6617885 (2003-09-01), Lim et al.
G.M. Yin et al, “A High-Speed CMOS Comparator with 8-b Resolution”, IEEE Journal of Solid-State Circuits, vol. 27, No. 2, Feb. 1992, pp. 208-211.

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